Searched refs:ST (Results 201 - 225 of 311) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h42 const R600Subtarget &ST; member in class:llvm::R600InstrFlags::final
H A DSIFixSGPRCopies.cpp590 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
592 TRI = ST.getRegisterInfo();
593 TII = ST.getInstrInfo();
691 if (ST.getConstantBusLimit(MI.getOpcode()) != 1)
H A DSIFoldOperands.cpp91 const GCNSubtarget *ST; member in class:__anon2113::SIFoldOperands
187 const GCNSubtarget &ST) {
196 ST.hasInv2PiInlineImm())) {
1241 if (updateOperand(Fold, *TII, *TRI, *ST)) {
1470 ST = &MF.getSubtarget<GCNSubtarget>();
1471 TII = ST->getInstrInfo();
184 updateOperand(FoldCandidate &Fold, const SIInstrInfo &TII, const TargetRegisterInfo &TRI, const GCNSubtarget &ST) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp555 const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(mf.getSubtarget()); local
556 if (!ST.hasLOB())
566 TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
567 TRI = ST.getRegisterInfo();
H A DARMParallelDSP.cpp273 auto *ST = &TM.getSubtarget<ARMSubtarget>(F); variable
275 if (!ST->allowsUnalignedMem()) {
281 if (!ST->hasDSP()) {
287 if (!ST->isLittle()) {
H A DARMFrameLowering.cpp2249 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>(); local
2250 bool Thumb = ST->isThumb();
2256 if (!ST->isTargetAndroid() && !ST->isTargetLinux())
2407 if (Thumb && ST->isThumb1Only()) {
2437 assert(ST->isTargetAndroid() || ST->isTargetLinux());
2438 unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
2531 if (ST->isThumb1Only()) {
2578 BuildMI(AllocMBB, DL, TII.get(ST
[all...]
H A DARMCallLowering.cpp270 auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>(); local
271 unsigned Opcode = ST.getReturnOpcode();
H A DThumbRegisterInfo.cpp130 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>(); local
162 } else if (ST.genExecuteOnly()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.h97 void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
H A DHexagonExpandCondsets.cpp688 MachineOperand &ST = MI.getOperand(2); local
690 if (ST.isReg() && SF.isReg()) {
691 RegisterRef RT(ST);
696 unsigned S = getRegState(ST);
709 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false);
H A DHexagonEarlyIfConv.cpp1052 auto &ST = MF.getSubtarget<HexagonSubtarget>();
1053 HII = ST.getInstrInfo();
1054 TRI = ST.getRegisterInfo();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp505 StructType *ST = cast<StructType>(WO->getType()); local
506 Constant *Struct = ConstantStruct::get(ST,
507 { UndefValue::get(ST->getElementType(0)),
508 ConstantInt::getFalse(ST->getElementType(1)) });
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineLICM.cpp342 const TargetSubtargetInfo &ST = MF.getSubtarget(); local
343 TII = ST.getInstrInfo();
344 TLI = ST.getTargetLowering();
345 TRI = ST.getRegisterInfo();
348 SchedModel.init(&ST);
H A DCodeGenPrepare.cpp3361 SimplificationTracker ST(SQ);
3366 InsertPlaceholders(Map, TraverseOrder, ST);
3369 FillPlaceholders(Map, TraverseOrder, ST);
3371 if (!AddrSinkNewSelects && ST.countNewSelectNodes() > 0) {
3372 ST.destroyNewNodes(CommonType);
3378 if (!MatchPhiSet(ST, AddrSinkNewPhis, PhiNotMatchedCount)) {
3379 ST.destroyNewNodes(CommonType);
3383 auto *Result = ST.Get(Map.find(Original)->second);
3385 NumMemoryInstsPhiCreated += ST.countNewPhiNodes() + PhiNotMatchedCount;
3386 NumMemoryInstsSelectCreated += ST
3446 MatchPhiSet(SimplificationTracker &ST, bool AllowNewPhiNodes, unsigned &PhiNotMatchedCount) argument
3493 FillPlaceholders(FoldAddrToValueMapping &Map, SmallVectorImpl<Value *> &TraverseOrder, SimplificationTracker &ST) argument
3529 InsertPlaceholders(FoldAddrToValueMapping &Map, SmallVectorImpl<Value *> &TraverseOrder, SimplificationTracker &ST) argument
6480 StoreInst *ST = cast<StoreInst>(CombineInst); local
[all...]
H A DMachineTraceMetrics.cpp68 const TargetSubtargetInfo &ST = MF->getSubtarget(); local
69 TII = ST.getInstrInfo();
70 TRI = ST.getRegisterInfo();
73 SchedModel.init(&ST);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1207 AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1208 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1209 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR ||
1210 ST == AArch64_AM::MSL);
1302 AArch64_AM::ShiftExtendType ST = getShiftExtendType();
1303 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1304 ST
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp6603 SDValue TargetLowering::scalarizeVectorStore(StoreSDNode *ST,
6605 SDLoc SL(ST);
6607 SDValue Chain = ST->getChain();
6608 SDValue BasePtr = ST->getBasePtr();
6609 SDValue Value = ST->getValue();
6610 EVT StVT = ST->getMemoryVT();
6648 return DAG.getStore(Chain, SL, CurrVal, BasePtr, ST->getPointerInfo(),
6649 ST->getAlignment(), ST->getMemOperand()->getFlags(),
6650 ST
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1706 MemSDNode *ST = cast<MemSDNode>(N);
1707 assert(ST->writeMem() && "Expected store");
1711 EVT StoreVT = ST->getMemoryVT();
1721 AtomicOrdering Ordering = ST->getOrdering();
1730 unsigned int CodeAddrSpace = getCodeAddrSpace(ST);
1732 CurDAG->getDataLayout().getPointerSizeInBits(ST->getAddressSpace());
1737 bool isVolatile = ST->isVolatile() || Ordering == AtomicOrdering::Monotonic;
1767 SDValue Chain = ST->getChain();
1769 SDValue BasePtr = ST->getBasePtr();
1877 SDNode *ST;
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp109 generateStackAdjustment(MBB, MBBI, *ST.getInstrInfo(), DebugLoc(),
182 generateStackAdjustment(MBB, MBBI, *ST.getInstrInfo(), dl,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DSafepointIRVerifier.cpp270 if (StructType *ST = dyn_cast<StructType>(Ty))
271 return llvm::any_of(ST->elements(), containsGCPtrType);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp34 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) argument
36 Subtarget(ST) {}
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DExprEngine.h595 SVal evalBinOp(ProgramStateRef ST, BinaryOperator::Opcode Op, argument
597 return svalBuilder.evalBinOp(ST, Op, LHS, RHS, T);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp30 VEFrameLowering::VEFrameLowering(const VESubtarget &ST) argument
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGRecordLayoutBuilder.cpp802 llvm::StructType *ST = RL->getLLVMType(); local
803 const llvm::StructLayout *SL = getDataLayout().getStructLayout(ST);
828 llvm::Type *ElementTy = ST->getTypeAtIndex(RL->getLLVMFieldNo(FD));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp697 const TargetSubtargetInfo &ST = MF.getSubtarget(); local
699 static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
702 SchedModel.init(&ST);

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