/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | GCNHazardRecognizer.cpp | 680 VDataRCID = Desc.OpInfo[VDataIdx].RegClass; 705 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256); 711 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
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H A D | SIPeepholeSDWA.cpp | 1185 if (Desc.OpInfo[I].RegClass == -1 || 1186 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
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H A D | AMDGPUISelDAGToDAG.cpp | 588 int RegClass = Desc.OpInfo[OpIdx].RegClass; local 589 if (RegClass == -1) 592 return Subtarget->getRegisterInfo()->getRegClass(RegClass); 686 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); local 690 RegClass);
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H A D | SIFoldOperands.cpp | 848 UseDesc.OpInfo[UseOpIdx].RegClass == -1) 864 TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 467 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 482 // Other RegClass doesn't need mapping
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H A D | PPCInstrInfo.cpp | 1360 if (UseInfo->RegClass /* Kind */ != 1) 1363 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && 1364 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) 1379 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1778 SDValue RegClass = local 1782 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1789 SDValue RegClass = local 1793 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1800 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, local 1804 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1811 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, local 1815 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1823 SDValue RegClass = local 1829 const SDValue Ops[] = { RegClass, V 1838 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, local 1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 167 unsigned findFreeReg(const TargetRegisterClass &RegClass); 580 /// Return the first register of class \p RegClass that is not in \p Regs. 581 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { argument 587 for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
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H A D | ARMFrameLowering.cpp | 1533 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); local 1534 if (RegClass && !RegClass->contains(ARM::SP))
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H A D | ARMBaseInstrInfo.cpp | 2433 const TargetRegisterClass *RegClass; local 2436 RegClass = &ARM::DPRRegClass; 2439 RegClass = &ARM::GPRRegClass; 2466 unsigned CurReg = RegClass->getRegister(CurRegEnc);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 313 unsigned &RegClass, unsigned &Cost, 326 RegClass = RC->getID(); 335 RegClass = RC->getID(); 343 RegClass = RC->getID(); 348 RegClass = TLI->getRepRegClassFor(VT)->getID(); 309 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
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H A D | FastISel.cpp | 2041 const TargetRegisterClass *RegClass = local 2043 if (!MRI.constrainRegClass(Op, RegClass)) { 2046 unsigned NewOp = createResultReg(RegClass);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64A57FPLoadBalancing.cpp | 518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 1953 if (Info.RegClass == X86::VR128RegClassID || 1954 Info.RegClass == X86::VR128XRegClassID) 1956 if (Info.RegClass == X86::VR256RegClassID || 1957 Info.RegClass == X86::VR256XRegClassID) 1959 if (Info.RegClass == X86::VR512RegClassID)
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H A D | X86ISelDAGToDAG.cpp | 4315 unsigned RegClass = getMaskRC(MaskVT); local 4316 SDValue RC = CurDAG->getTargetConstant(RegClass, dl, MVT::i32); 4353 unsigned RegClass = getMaskRC(ResVT); local 4354 SDValue RC = CurDAG->getTargetConstant(RegClass, dl, MVT::i32);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveIntervals.cpp | 1671 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); local 1673 Register NewVReg = MRI->createVirtualRegister(RegClass);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 822 if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
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H A D | HexagonMCChecker.cpp | 456 if (Desc.OpInfo[std::get<1>(Producer)].RegClass ==
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineRegisterInfo.h | 720 Register createVirtualRegister(const TargetRegisterClass *RegClass,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 1768 // register (or frame index) operand if MCOI.RegClass contains a valid 1771 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) || 1772 (MCOI.RegClass == -1 && !Op.isImm()))) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 1139 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUInstPrinter.cpp | 579 int RCID = Desc.OpInfo[OpNo].RegClass;
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenDAGPatterns.cpp | 1669 RC = Operand->getValueAsDef("RegClass"); 2135 Record *RegClass = R->getValueAsDef("RegClass"); 2137 return TypeSetByHwMode(T.getRegisterClass(RegClass).getValueTypes());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 3668 int16_t DstRegClass = Desc.OpInfo[StartOp].RegClass; 3795 int16_t DstRegClass = Desc.OpInfo[StartOp].RegClass;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 6229 && Desc.OpInfo[OpNum + 1].RegClass != -1
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