Searched refs:RC (Results 76 - 100 of 324) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp182 static wasm::ValType getType(const TargetRegisterClass *RC) { argument
183 if (RC == &WebAssembly::I32RegClass)
185 if (RC == &WebAssembly::I64RegClass)
187 if (RC == &WebAssembly::F32RegClass)
189 if (RC == &WebAssembly::F64RegClass)
191 if (RC == &WebAssembly::V128RegClass)
H A DWebAssemblyFastISel.cpp660 const TargetRegisterClass *RC; local
667 RC = &WebAssembly::I32RegClass;
671 RC = &WebAssembly::I64RegClass;
675 RC = &WebAssembly::F32RegClass;
679 RC = &WebAssembly::F64RegClass;
683 RC = &WebAssembly::V128RegClass;
687 RC = &WebAssembly::V128RegClass;
691 RC = &WebAssembly::V128RegClass;
695 RC = &WebAssembly::V128RegClass;
699 RC
907 const TargetRegisterClass *RC; local
1170 const TargetRegisterClass *RC; local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.h80 const TargetRegisterClass *RC,
84 int FrameIndex, const TargetRegisterClass *RC,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h58 const TargetRegisterClass *RC,
65 const TargetRegisterClass *RC,
H A DMipsSEInstrInfo.h52 const TargetRegisterClass *RC,
59 const TargetRegisterClass *RC,
H A DMipsMachineFunction.h79 int getMoveF64ViaSpillFI(const TargetRegisterClass *RC);
H A DMipsRegisterInfo.h50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
H A DMipsOptimizePICCall.cpp139 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local
140 assert(TRI.legalclasstypes_end(*RC) - TRI.legalclasstypes_begin(*RC) == 1);
141 return *TRI.legalclasstypes_begin(*RC);
H A DMips16ISelDAGToDAG.cpp76 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local
78 V0 = RegInfo.createVirtualRegister(RC);
79 V1 = RegInfo.createVirtualRegister(RC);
80 V2 = RegInfo.createVirtualRegister(RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp248 LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
340 const int Def = RDA->getReachingDef(mi, RC->getRegister(rx));
342 return RDA->getReachingDef(mi, RC->getRegister(I)) <= Def;
420 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
423 << TRI->getRegClassName(RC) << " **********\n");
429 for (unsigned Reg : *RC) {
442 // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
445 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
446 for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true); AI.isValid();
H A DTargetInstrInfo.cpp379 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, argument
385 Size = TRI->getSpillSize(*RC);
401 assert(TRI->getSpillSize(*RC) >= (Offset + Size) && "bad subregister range");
404 Offset = TRI->getSpillSize(*RC) - (Offset + Size);
453 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local
456 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
458 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
459 return RC;
515 const TargetRegisterClass *RC local
606 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); local
782 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); local
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H A DCriticalAntiDepBreaker.h106 const TargetRegisterClass *RC,
H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
60 VRegInfo[Reg].first = RC;
71 const TargetRegisterClass *RC, unsigned MinNumRegs) {
72 if (OldRC == RC)
73 return RC;
75 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
86 const TargetRegisterClass *RC,
69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, const TargetRegisterClass *OldRC, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
85 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp25 const MCRegisterClass *RC) const {
27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.h316 // R:SubRegIndex in this RC for all R in SuperRC.
364 // Returns true if RC is a subclass.
365 // RC is a sub-class of this class if it is a valid replacement for any
369 // 1. All RC registers are also in this.
370 // 2. The RC spill size must not be smaller than our spill size.
371 // 3. RC spill alignment must be compatible with ours.
373 bool hasSubClass(const CodeGenRegisterClass *RC) const {
374 return SubClasses.test(RC->EnumValue);
456 Key(const CodeGenRegisterClass &RC) argument
457 : Members(&RC
585 inferMatchingSuperRegClass(CodeGenRegisterClass *RC) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); local
162 if (RC == nullptr) {
165 } else if (RC->contains(AArch64::WZR))
167 else if (RC->contains(AArch64::XZR))
H A DAArch64RegisterInfo.cpp103 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, argument
106 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub)
108 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub)
112 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
258 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
259 if (RC == &AArch64::CCRRegClass)
261 return RC;
540 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
544 switch (RC->getID()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h59 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.h67 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h117 int FrameIdx, const TargetRegisterClass *RC,
121 const TargetRegisterClass *RC,
289 const TargetRegisterClass *RC,
295 const TargetRegisterClass *RC,
299 const TargetRegisterClass *RC = nullptr) const;
302 const TargetRegisterClass *RC = nullptr) const;
401 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
H A DPPCInstrInfo.cpp769 const TargetRegisterClass *RC = local
771 if (!RC)
775 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
776 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
777 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
778 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
802 const TargetRegisterClass *RC = local
804 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
806 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
807 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
1199 StoreRegToStackSlot( MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const argument
1224 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
1255 LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs) const argument
1277 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/
H A DRawCommentList.cpp272 void RawCommentList::addComment(const RawComment &RC, argument
275 if (RC.isInvalid())
279 if (RC.isOrdinary() && !CommentOpts.ParseAllComments)
283 SourceMgr.getDecomposedLoc(RC.getBeginLoc());
292 new (Allocator) RawComment(RC);
297 const RawComment &C2 = RC;
323 new (Allocator) RawComment(RC);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp296 GISelInstProfileBuilder::addNodeIDRegType(const TargetRegisterClass *RC) const {
297 ID.AddPointer(RC);
350 auto *RC = MRI.getRegClassOrNull(Reg); local
351 if (RC)
352 addNodeIDRegType(RC);
H A DRegisterBankInfo.cpp95 if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
96 return &getRegBankFromRegClass(*RC, MRI.getType(Reg));
119 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); local
121 if (!RC)
125 const RegisterBank &RegBank = getRegBankFromRegClass(*RC, MRI.getType(Reg));
127 assert(RegBank.covers(*RC) &&
133 Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
138 return MRI.constrainRegClass(Reg, &RC);
142 if (RB && !RB->covers(RC))
146 MRI.setRegClass(Reg, &RC);
132 constrainGenericRegister( Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) argument
502 auto *RC = &getMinimalPhysRegClass(Reg, TRI); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1270 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local
1271 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1334 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local
1336 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI);
1428 /// Returns true if there are no caller-saved registers available in class RC.
1430 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1442 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
1550 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); local
1551 int FI = MFI.CreateFixedSpillStackObject(TRI->getSpillSize(*RC), S->Offset);
1562 const TargetRegisterClass *RC local
1429 needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) argument
1698 auto *RC = &Hexagon::HvxVRRegClass; local
1734 auto *RC = &Hexagon::HvxVRRegClass; local
2079 const TargetRegisterClass *RC = nullptr; member in struct:SlotInfo
2141 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF); local
2309 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); local
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