Searched refs:Pred (Results 176 - 200 of 335) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp995 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); local
996 unsigned PredCond = PPC::getPredicateCondition(Pred);
1033 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
1034 unsigned PredCond = PPC::getPredicateCondition(Pred);
1035 unsigned PredHint = PPC::getPredicateHint(Pred);
1052 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
1053 unsigned PredCond = PPC::getPredicateCondition(Pred);
1054 unsigned PredHint = PPC::getPredicateHint(Pred);
1335 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); local
1336 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred);
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H A DPPCInstrInfo.h341 ArrayRef<MachineOperand> Pred) const override;
347 std::vector<MachineOperand> &Pred) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DBranchFolding.cpp899 for (MachineBasicBlock *Pred : MBB->predecessors()) {
901 LiveRegs.addLiveOuts(*Pred);
902 MachineBasicBlock::iterator InsertBefore = Pred->getFirstTerminator();
907 BuildMI(*Pred, InsertBefore, DL, TII->get(TargetOpcode::IMPLICIT_DEF),
1397 MachineBasicBlock *Pred = *(MBB->pred_end()-1); local
1398 Pred->ReplaceUsesOfBlockWith(MBB, &*FallThrough);
1559 MachineBasicBlock *Pred = *MBB->pred_begin(); local
1563 !TII->analyzeBranch(*Pred, PredTBB, PredFBB, PredCond, true);
1574 TII->replaceBranchWithTailCall(*Pred, PredCond, TailCall);
1576 Pred
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H A DLiveIntervals.cpp406 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
407 if (!LiveOut.insert(Pred).second)
409 SlotIndex Stop = Indexes->getMBBEndIdx(Pred);
422 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
423 if (!LiveOut.insert(Pred).second)
425 SlotIndex Stop = Indexes->getMBBEndIdx(Pred);
438 assert(LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes) &&
857 for (const MachineBasicBlock *Pred : PHIMBB->predecessors())
858 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(Pred)))
H A DHardwareLoops.cpp346 BasicBlock *Pred = Preheader->getSinglePredecessor();
347 if (!isa<BranchInst>(Pred->getTerminator()))
350 auto *BI = cast<BranchInst>(Pred->getTerminator());
H A DAnalysis.cpp201 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { argument
202 switch (Pred) {
238 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { argument
239 switch (Pred) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp1068 BasicBlock *Pred = PN->getIncomingBlock(i); local
1069 Value *&PredVal = PredValues[Pred];
1073 EltPHI->addIncoming(PredVal, Pred);
1081 EltPHI->addIncoming(PredVal, Pred);
1090 EltPHI->addIncoming(PredVal, Pred);
1096 Builder.SetInsertPoint(Pred->getTerminator());
1103 EltPHI->addIncoming(Res, Pred);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DLoopInfo.h238 for (const auto Pred : children<Inverse<BlockT *>>(H))
239 if (contains(Pred))
317 for (const auto Pred : children<Inverse<BlockT *>>(H))
318 if (contains(Pred))
319 LoopLatches.push_back(Pred);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp461 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
473 .add(predOps(Pred, PredReg))
809 ARMCC::CondCodes Pred = (PIdx == -1) local
825 Offset, Pred, PredReg, TII);
829 Offset, Pred, PredReg, TII);
458 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DARMBaseInstrInfo.cpp179 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm(); local
194 .add(predOps(Pred))
205 .add(predOps(Pred))
212 .add(predOps(Pred))
225 .add(predOps(Pred))
232 .add(predOps(Pred))
245 .addImm(Pred);
252 .addImm(Pred);
261 .addImm(Pred);
268 .addImm(Pred);
2000 MachineBasicBlock *Pred = *MBB.pred_begin(); local
2354 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp288 /// Examine Pred and see if it is possible to insert an instruction into
290 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
921 bool MipsDelaySlotFiller::examinePred(MachineBasicBlock &Pred, argument
927 getBranch(Pred, Succ);
937 RegDU.addLiveOut(Pred, Succ);
940 BrMap[&Pred] = P.second;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DMergeICmps.cpp726 BasicBlock* const Pred = *pred_begin(EntryBlock_); local
727 LLVM_DEBUG(dbgs() << "Updating jump into old chain from " << Pred->getName()
729 Pred->getTerminator()->replaceUsesOfWith(EntryBlock_, NextCmpBlock);
730 DTU.applyUpdates({{DominatorTree::Delete, Pred, EntryBlock_},
731 {DominatorTree::Insert, Pred, NextCmpBlock}});
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp536 const TreePredicateCall &Pred = N->getPredicateCalls()[i]; local
538 if (Pred.Fn.usesOperands()) {
539 TreePattern *TP = Pred.Fn.getOrigPatFragRecord();
542 ("pred:" + Twine(Pred.Scope) + ":" + TP->getArgName(i)).str();
546 AddMatcher(new CheckPredicateMatcher(Pred.Fn, Operands));
H A DDAGISelMatcher.cpp97 : Matcher(CheckPredicate), Pred(pred.getOrigPatFragRecord()),
101 return TreePredicateFn(Pred);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp428 RegisterSubReg Pred = getPredRegFor(GPR); local
429 MIB.addReg(Pred.R, 0, Pred.S);
H A DHexagonRegisterInfo.cpp65 static const MCPhysReg Pred[] = { local
86 return Pred;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/
H A DObjCARCContract.cpp483 BasicBlock *Pred = InstParent->getSinglePredecessor(); local
484 if (!Pred)
486 BBI = Pred->getTerminator()->getIterator();
/freebsd-11-stable/contrib/libstdc++/include/ext/pb_ds/detail/ov_tree_map_/
H A Dov_tree_map_.hpp338 template<typename Pred>
340 erase_if(Pred);
/freebsd-11-stable/contrib/libstdc++/include/ext/pb_ds/detail/pat_trie_/
H A Dpat_trie_.hpp289 template<typename Pred>
291 erase_if(Pred);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSSAUpdater.cpp287 static void AddPHIOperand(PHINode *PHI, Value *Val, BasicBlock *Pred) { argument
288 PHI->addIncoming(Val, Pred);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/
H A DCore.cpp84 typename Pred = PrintAll<typename Sequence::value_type>>
88 Pred ShouldPrint = Pred())
110 mutable Pred ShouldPrint;
113 template <typename Sequence, typename Pred>
114 SequencePrinter<Sequence, Pred> printSequence(const Sequence &S, char OpenSeq, argument
115 char CloseSeq, Pred P = Pred()) {
116 return SequencePrinter<Sequence, Pred>(S, OpenSeq, CloseSeq, std::move(P));
120 template <typename Sequence, typename Pred>
87 SequencePrinter(const Sequence &S, char OpenSeq, char CloseSeq, Pred ShouldPrint = Pred()) argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp343 CmpInst::Predicate Pred = local
346 if (CmpInst::isIntPredicate(Pred))
347 MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
348 else if (Pred == CmpInst::FCMP_FALSE)
351 else if (Pred == CmpInst::FCMP_TRUE)
356 MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1},
592 Cond = MIB.buildICmp(CB.PredInfo.Pred, i1Ty, CondLHS, CondRHS).getReg(0);
594 assert(CB.PredInfo.Pred == CmpInst::ICMP_SLE &&
725 CmpInst::Predicate Pred; local
728 Pred
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h158 const MachineBasicBlock *Pred = nullptr; member in struct:llvm::MachineTraceMetrics::TraceBlockInfo
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DBasicBlockUtils.h88 /// if BB's Pred has a branch to BB and to AnotherBB, and BB has a single
281 BasicBlock *Pred,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h244 ArrayRef<MachineOperand> Pred) const override;

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