/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.h | 51 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 51 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 377 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, argument 385 if (!SelectADDRrr(Op, Op0, Op1)) 386 SelectADDRri(Op, Op0, Op1);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 272 const Value *Op = GTI.getOperand(); local 275 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 280 if (const auto *CI = dyn_cast<ConstantInt>(Op)) { 287 unsigned Reg = getRegForValue(Op); 293 if (canFoldAddIntoGEP(U, Op)) { 295 auto *CI = cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 298 Op = cast<AddOperator>(Op)->getOperand(0); 968 const Value *Op = ZExt->getOperand(0); local 969 MVT::SimpleValueType From = getSimpleType(Op 985 const Value *Op = SExt->getOperand(0); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIMemoryLegalizer.cpp | 287 /// to instruction \p MI to ensure memory instructions of kind \p Op 296 SIMemOp Op, 338 SIMemOp Op, 384 SIMemOp Op, 758 SIMemOp Op, 1008 SIMemOp Op, 1027 if ((Op & SIMemOp::LOAD) != SIMemOp::NONE) 1029 if ((Op & SIMemOp::STORE) != SIMemOp::NONE) 1039 if ((Op & SIMemOp::LOAD) != SIMemOp::NONE) 1041 if ((Op 755 insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope, SIAtomicAddrSpace AddrSpace, SIMemOp Op, bool IsCrossAddrSpaceOrdering, Position Pos) const argument 1005 insertWait(MachineBasicBlock::iterator &MI, SIAtomicScope Scope, SIAtomicAddrSpace AddrSpace, SIMemOp Op, bool IsCrossAddrSpaceOrdering, Position Pos) const argument [all...] |
H A D | GCNRegBankReassign.cpp | 362 for (const auto& Op : MI.explicit_uses()) { 365 if (!Op.isReg() || Op.isUndef()) 368 Register R = Op.getReg(); 374 if (Bank != -1 && R == Reg && Op.getSubReg()) { 375 unsigned LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()).getAsInteger(); 391 unsigned Mask = getRegBankMask(R, Op.getSubReg(), 395 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask));
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H A D | SILowerControlFlow.cpp | 446 MachineOperand &Op = MI.getOperand(OpNo); local 447 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) { 448 Src.push_back(Op); 452 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local 37 GetExpandedOp(Op, Lo, Hi); 310 void DAGTypeLegalizer::IntegerToVector(SDValue Op, unsigned NumElements, argument 313 assert(Op.getValueType().isInteger()); 314 SDLoc DL(Op); 319 SplitInteger(Op, Parts[0], Parts[1]); 325 Ops.push_back(DAG.getNode(ISD::BITCAST, DL, EltVT, Op)); 501 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local 502 GetSplitOp(Op, Lo, Hi);
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H A D | LegalizeVectorTypes.cpp | 271 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local 272 return GetScalarizedVector(Op); 276 SDValue Op = N->getOperand(0); local 277 if (Op.getValueType().isVector() 278 && Op.getValueType().getVectorNumElements() == 1 279 && !isSimpleLegalType(Op.getValueType())) 280 Op = GetScalarizedVector(Op); 283 NewVT, Op); 304 SDValue Op local 310 SDValue Op = GetScalarizedVector(N->getOperand(0)); local 318 SDValue Op = N->getOperand(1); local 346 SDValue Op = N->getOperand(0); local 377 SDValue Op = N->getOperand(0); local 506 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue(); local 651 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), local 1274 SDValue Op = N->getOperand(i); local 3113 SDValue Op = InOps[i]; local 3140 SDValue Op = InOps[i]; local 4683 SDValue Op = GetWidenedVector(N->getOperand(0)); local [all...] |
H A D | SelectionDAGISel.cpp | 400 for (const auto &Op : I.operands()) { 401 if (Op->getType()->isFPOrFPVectorTy()) { 752 for (const SDValue &Op : N->op_values()) 753 if (Op.getValueType() == MVT::Other && Added.insert(Op.getNode()).second) 754 Worklist.push_back(Op.getNode()); 1136 for (const SDValue &Op : N->op_values()) { 1137 if (Op->getOpcode() == ISD::TokenFactor) 1138 Nodes.push_back(Op.getNode()); 1148 assert(Op 2250 Select_READ_REGISTER(SDNode *Op) argument 2267 Select_WRITE_REGISTER(SDNode *Op) argument [all...] |
H A D | LegalizeDAG.cpp | 182 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl); 183 SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl); 185 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 186 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 973 for (const SDValue &Op : Node->op_values()) 974 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == 976 Op.getOpcode() == ISD::TargetConstant || 977 Op.getOpcode() == ISD::Register) && 1284 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1285 SDValue Vec = Op [all...] |
H A D | SelectionDAGPrinter.cpp | 97 SDValue Op = EI.getNode()->getOperand(EI.getOperand()); local 98 EVT VT = Op.getValueType();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86DomainReassignment.cpp | 158 for (auto &Op : MI->explicit_operands()) 159 Bld.add(Op); 540 auto &Op = MI.getOperand(MemOpIdx); local 541 if (Op.isReg() && Op.getReg() == Reg) 576 auto &Op = DefMI->getOperand(OpIdx); local 577 if (!Op.isReg() || !Op.isUse()) 579 visitRegister(C, Op.getReg(), Domain, Worklist);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstructionCombining.cpp | 532 /// it just returns the 'Op' inputs. But for special-cases like 534 /// and Op = shl(X, 5). The 'shl' is treated as the more general 'mul X, 32' to 537 getBinOpsForFactorization(Instruction::BinaryOps TopOpcode, BinaryOperator *Op, argument 539 assert(Op && "Expected a binary operator"); 540 LHS = Op->getOperand(0); 541 RHS = Op->getOperand(1); 544 if (match(Op, m_Shl(m_Value(), m_Constant(C)))) { 546 RHS = ConstantExpr::getShl(ConstantInt::get(Op->getType(), 1), C); 551 return Op->getOpcode(); 889 Instruction *InstCombiner::FoldOpIntoSelect(Instruction &Op, SelectIns argument 2497 Value *Op = FI.getArgOperand(0); local 2562 Value *Op = FI.getArgOperand(0); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | Metadata.cpp | 509 unsigned Op = 0; local 511 setOperand(Op++, MD); 513 setOperand(Op++, MD); 534 static bool isOperandUnresolved(Metadata *Op) { argument 535 if (auto *N = dyn_cast_or_null<MDNode>(Op)) 551 for (auto &Op : mutable_operands()) 552 Op.reset(Op.get(), this); 630 for (const auto &Op : operands()) { 631 auto *N = dyn_cast_or_null<MDNode>(Op); 701 unsigned Op = static_cast<MDOperand *>(Ref) - op_begin(); local [all...] |
H A D | DebugInfo.cpp | 285 if (std::none_of(N->op_begin() + 1, N->op_end(), [](const MDOperand &Op) { 286 return isa<DILocation>(Op.get()); 292 if (std::none_of(N->op_begin() + 1, N->op_end(), [](const MDOperand &Op) { 293 return !isa<DILocation>(Op.get()); 302 for (auto Op = N->op_begin() + 1; Op != N->op_end(); Op++) { 303 if (!isa<DILocation>(*Op)) 304 Args.push_back(*Op); 668 for (MDNode *Op [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 305 bool SelectInlineAsmMemoryOperand(const SDValue &Op, 322 SDLoc dl(Op); 326 dl, Op.getValueType(), 327 Op, RC), 0); 4047 SDValue Op = N->getOperand(0); local 4051 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 4052 SDValue Ops[] = { Op, getI32Imm(27, dl), getI32Imm(5, dl), 4061 Op, getI32Imm(~0U, dl)), 0); 4062 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, A 4082 SDValue Op = N->getOperand(0); local 4567 SDValue Op = N->getOperand(1); local 4607 SDNode *Op = local 4616 SDNode *Op = local 5719 SDValue Op = MachineNode->getOperand(1); local 5746 SDValue Op = MachineNode->getOperand(0); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RDFLiveness.cpp | 885 for (auto &Op : MI->operands()) { 890 if (!Op.isReg() || !Op.isDef() || Op.isImplicit()) 892 Register R = Op.getReg(); 898 for (auto &Op : MI->operands()) { 899 if (!Op.isReg() || !Op.isUse() || Op.isUndef()) 901 Register R = Op [all...] |
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/ASTMatchers/Dynamic/ |
H A D | VariantValue.h | 110 constructVariadicOperator(DynTypedMatcher::VariadicOperator Op, 151 VariadicOperatorMatcher(DynTypedMatcher::VariadicOperator Op,
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | User.h | 133 template <int Idx> Use &Op() { 136 template <int Idx> const Use &Op() const {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsISelDAGToDAG.cpp | 311 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, argument 320 OutOps.push_back(Op);
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/ |
H A D | LoopUtils.h | 303 getOrderedReduction(IRBuilder<> &Builder, Value *Acc, Value *Src, unsigned Op, 310 Value *getShuffleReduction(IRBuilder<> &Builder, Value *Src, unsigned Op,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86IntelInstPrinter.h | 43 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); 47 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O);
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | GICombinerEmitter.cpp | 120 const GIMatchDagOperand *Op; member in struct:__anon2928::CombineRule::VarInfo 124 VarInfo(const GIMatchDagInstr *N, const GIMatchDagOperand *Op, argument 126 : N(N), Op(Op), Matcher(Matcher) {} 550 MatchDag.addEdge(insertStrTab(NameAndDefs.getKey()), UseVar.N, UseVar.Op, 551 DefVar.N, DefVar.Op); 585 MatchDag.addPredicateDependency(LeadingVar.N, LeadingVar.Op, P, 587 MatchDag.addPredicateDependency(Var.N, Var.Op, P,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
H A D | SimplifyLibCalls.cpp | 1281 Value *Op = Cast->getOperand(0); 1282 if (Op->getType()->isFloatTy()) 1283 return Op; 1377 Value *Op = CI->getArgOperand(0); 1378 assert(Op->getType()->isArrayTy() && "Unexpected signature for cabs!"); 1379 Real = B.CreateExtractValue(Op, 0, "real"); 1380 Imag = B.CreateExtractValue(Op, 1, "imag"); 1458 Value *Op = cast<Instruction>(I2F)->getOperand(0); 1461 unsigned BitWidth = Op->getType()->getPrimitiveSizeInBits(); 1464 return isa<SIToFPInst>(I2F) ? B.CreateSExt(Op, [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 1487 for (const auto &Op : x86OperandSets[insn->spec->operands]) { 1488 switch (Op.encoding) { 1514 switch ((OperandType)Op.type) { 1533 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) 1534 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB); 1540 if (fixupReg(insn, &Op)) 1543 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) 1544 insn->displacement *= 1 << (Op.encoding - ENCODING_RM); 1557 if (Op.type == TYPE_XMM || Op [all...] |