Searched refs:MBB (Results 126 - 150 of 513) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineBranchProbabilityInfo.cpp70 MachineBranchProbabilityInfo::getHotSucc(MachineBasicBlock *MBB) const {
73 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
74 E = MBB->succ_end(); I != E; ++I) {
75 auto Prob = getEdgeProbability(MBB, I);
83 if (getEdgeProbability(MBB, MaxSucc) >= HotProb)
H A DSlotIndexes.cpp54 // Iterate over all MBBs, and within each MBB all MIs, keeping the MI
68 "Index -> MBB mapping non-empty at initial numbering?");
70 "MBB -> Index mapping non-empty at initial numbering?");
81 for (MachineBasicBlock &MBB : *mf) {
82 // Insert an index for the MBB start.
85 for (MachineInstr &MI : MBB) {
100 MBBRanges[MBB.getNumber()].first = blockStartIndex;
101 MBBRanges[MBB.getNumber()].second = SlotIndex(&indexList.back(),
103 idx2MBBMap.push_back(IdxMBBPair(blockStartIndex, &MBB));
178 void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB, argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp83 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
245 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, argument
250 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
296 const Function &Func = MBB.getParent()->getFunction();
299 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
302 BuildMI(MBB,
319 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
404 MachineBasicBlock &MBB = *MI.getParent(); local
575 adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
603 loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const argument
672 expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
690 expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
707 expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned NewOpc) const argument
713 expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned LoOpc, unsigned HiOpc, bool HasExplicitDef) const argument
743 expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned CvtOpc, unsigned MovOpc, bool IsI64) const argument
767 expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool isMicroMips, bool FP64) const argument
870 expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
[all...]
H A DMipsMachineFunction.cpp66 MachineBasicBlock &MBB = MF.front();
67 MachineBasicBlock::iterator I = MBB.begin();
82 MBB.addLiveIn(Mips::T9_64);
88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
102 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
110 MBB.addLiveIn(Mips::T9);
117 BuildMI(MBB,
[all...]
H A DMips16RegisterInfo.cpp57 (MachineBasicBlock &MBB,
63 const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
64 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
65 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
134 MachineBasicBlock &MBB = *MI.getParent(); local
139 FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
56 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
H A DMipsDelaySlotFiller.cpp121 /// Set bits in Uses corresponding to MBB's live-out registers except for
123 void addLiveOut(const MachineBasicBlock &MBB,
248 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
250 Iter replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
262 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
268 bool searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const;
270 /// This function searches MBB in the forward direction for an instruction
272 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
274 /// This function searches one of MBB's successor blocks for an instruction
277 bool searchSuccBBs(MachineBasicBlock &MBB, Ite
325 addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) argument
403 addLiveOut(const MachineBasicBlock &MBB, const MachineBasicBlock &SuccBB) argument
560 replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch, const DebugLoc &DL) argument
602 runOnMachineBasicBlock(MachineBasicBlock &MBB) argument
689 searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot, IterTy &Filler) const argument
771 searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const argument
791 MBB.splice(std::next(SlotI), &MBB, Filler.getReverse()); local
797 searchForward(MachineBasicBlock &MBB, Iter Slot) const argument
815 MBB.splice(std::next(Slot), &MBB, Filler); local
821 searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const argument
885 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp166 MachineBasicBlock *MBB = Worklist.pop_back_val(); local
168 if (MBB == EMBB || !Visited.insert(MBB).second)
170 for(auto &Term : MBB->terminators())
174 Worklist.append(MBB->succ_begin(), MBB->succ_end());
181 MachineBasicBlock *MBB = MI->getParent(); local
190 if (J != MBB->end() && J->getOpcode() == FalseTermOpc &&
199 MachineBasicBlock &MBB = *MI.getParent(); local
219 BuildMI(MBB,
282 MachineBasicBlock &MBB = *MI.getParent(); local
355 MachineBasicBlock &MBB = *MI.getParent(); local
399 MachineBasicBlock &MBB = *MI.getParent(); local
420 MachineBasicBlock &MBB = *MI.getParent(); local
531 MachineBasicBlock &MBB = *BI; local
[all...]
H A DSIFrameLowering.cpp92 static void buildPrologSpill(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB, argument
96 MachineFunction *MF = MBB.getParent();
106 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFSET))
123 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
126 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFEN))
140 static void buildEpilogReload(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB, argument
144 MachineFunction *MF = MBB.getParent();
153 BuildMI(MBB, I, DebugLoc(),
170 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
173 BuildMI(MBB,
533 emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF, MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI, MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg, unsigned ScratchRsrcReg) const argument
1091 eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
[all...]
H A DSIWholeQuadMode.cpp139 MachineBasicBlock *MBB = nullptr; member in struct:__anon2132::WorkItem
143 WorkItem(MachineBasicBlock *MBB) : MBB(MBB) {} argument
170 void propagateBlock(MachineBasicBlock &MBB, std::vector<WorkItem> &Worklist);
175 MachineBasicBlock::iterator saveSCC(MachineBasicBlock &MBB,
178 prepareInsertion(MachineBasicBlock &MBB, MachineBasicBlock::iterator First,
181 void toExact(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
183 void toWQM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
185 void toWWM(MachineBasicBlock &MBB, MachineBasicBloc
325 MachineBasicBlock &MBB = **BI; local
430 MachineBasicBlock *MBB = MI.getParent(); local
475 propagateBlock(MachineBasicBlock &MBB, std::vector<WorkItem>& Worklist) argument
559 saveSCC(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before) argument
580 prepareInsertion( MachineBasicBlock &MBB, MachineBasicBlock::iterator First, MachineBasicBlock::iterator Last, bool PreferLast, bool SaveSCC) argument
628 toExact(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before, unsigned SaveWQM, unsigned LiveMaskReg) argument
650 toWQM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before, unsigned SavedWQM) argument
669 toWWM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before, unsigned SaveOrig) argument
680 fromWWM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before, unsigned SavedOrig) argument
692 processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg, bool isEntry) argument
[all...]
H A DR600InstrInfo.h48 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
54 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
75 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
78 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
167 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
172 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
177 unsigned removeBranch(MachineBasicBlock &MBB,
184 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
187 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
244 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
[all...]
H A DSIInsertSkips.cpp63 MachineBasicBlock *insertSkipBlock(MachineBasicBlock &MBB,
66 bool skipMaskBranch(MachineInstr &MI, MachineBasicBlock &MBB);
115 const MachineBasicBlock &MBB = *MBBI; local
117 for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
150 MachineBasicBlock &MBB = *MI.getParent(); local
151 MachineFunction *MF = MBB.getParent();
154 !shouldSkip(MBB, MBB.getParent()->back()))
157 MachineBasicBlock *SkipBB = insertSkipBlock(MBB, M
185 MachineBasicBlock &MBB = *MI.getParent(); local
306 insertSkipBlock( MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
345 MachineBasicBlock &MBB = *MI.getParent(); local
448 MachineBasicBlock &MBB = *BI; local
[all...]
H A DSIFixVGPRCopies.cpp54 for (MachineBasicBlock &MBB : MF) {
55 for (MachineInstr &MI : MBB) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp47 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
84 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
88 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
106 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { argument
108 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>();
111 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
119 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
137 MachineBasicBlock::iterator D = MBB
167 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot) argument
480 tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp46 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
75 bool findDelayInstr(MachineBasicBlock &MBB,
91 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { argument
93 LastFiller = MBB.instr_end();
95 for (MachineBasicBlock::instr_iterator I = MBB.instr_begin();
96 I != MBB.instr_end(); ++I) {
120 MBB.splice(std::next(I), &MBB, FI, I); local
123 if (!NopDelaySlotFiller && findDelayInstr(MBB, I, J)) {
124 MBB local
144 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator Slot, MachineBasicBlock::instr_iterator &Filler) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp38 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, argument
43 MachineFunction &MF = *MBB.getParent();
51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
68 BuildMI(MBB, I, DL, get(ARM::tPUSH))
71 BuildMI(MBB, I, DL, get(ARM::tPOP))
78 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, argument
89 if (I != MBB.end()) DL = I->getDebugLoc();
91 MachineFunction &MF = *MBB
106 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
H A DThumbRegisterInfo.cpp61 static void emitThumb1LoadConstPool(MachineBasicBlock &MBB, argument
67 MachineFunction &MF = *MBB.getParent();
72 Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), Val);
75 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
81 static void emitThumb2LoadConstPool(MachineBasicBlock &MBB, argument
87 MachineFunction &MF = *MBB.getParent();
91 Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), Val);
94 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
104 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
107 MachineFunction &MF = *MBB
103 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
124 emitThumbRegPlusImmInReg( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
186 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags) argument
[all...]
H A DA15SDOptimizer.cpp66 unsigned createDupLane(MachineBasicBlock &MBB,
71 unsigned createExtractSubreg(MachineBasicBlock &MBB,
76 unsigned createVExt(MachineBasicBlock &MBB,
80 unsigned createRegSequence(MachineBasicBlock &MBB,
85 unsigned createInsertSubreg(MachineBasicBlock &MBB,
90 unsigned createImplicitDef(MachineBasicBlock &MBB,
416 unsigned A15SDOptimizer::createDupLane(MachineBasicBlock &MBB, argument
422 BuildMI(MBB, InsertBefore, DL,
433 MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
437 BuildMI(MBB,
432 createExtractSubreg( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
447 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) argument
464 createVExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1) argument
477 createInsertSubreg( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument
493 createImplicitDef(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL) argument
511 MachineBasicBlock &MBB = *MI->getParent(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp361 const MachineBasicBlock &MBB = *BI; local
362 if (!MBB.isReturnBlock())
364 const MachineInstr &Ret = MBB.back();
597 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
599 - If MBB is not an entry block, initialize the register scavenger and look
613 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, argument
631 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
632 if ((UseAtEnd && MBB->isReturnBlock()) ||
633 (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
2184 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
2272 restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) argument
2308 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const argument
2347 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86WinAllocaExpander.cpp138 for (MachineBasicBlock &MBB : MF)
139 OutOffset[&MBB] = INT32_MAX;
148 for (MachineBasicBlock *MBB : RPO) {
150 for (MachineBasicBlock *Pred : MBB->predecessors())
154 for (MachineInstr &MI : *MBB) {
187 OutOffset[MBB] = Offset;
199 MachineBasicBlock *MBB = MI->getParent(); local
220 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
234 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
238 BuildMI(*MBB,
[all...]
H A DX86SpeculativeLoadHardening.cpp140 MachineBasicBlock *MBB; member in struct:__anon2518::X86SpeculativeLoadHardeningPass::BlockCondInfo
182 unsigned saveEFLAGS(MachineBasicBlock &MBB,
184 void restoreEFLAGS(MachineBasicBlock &MBB,
188 void mergePredStateIntoSP(MachineBasicBlock &MBB,
191 unsigned extractPredStateFromSP(MachineBasicBlock &MBB,
203 unsigned hardenValueInRegister(unsigned Reg, MachineBasicBlock &MBB,
223 static MachineBasicBlock &splitEdge(MachineBasicBlock &MBB, argument
229 MachineFunction &MF = *MBB.getParent();
236 MF.insert(std::next(MachineFunction::iterator(&MBB)), &NewMBB);
250 assert(MBB
699 MachineBasicBlock &MBB = *Info.MBB; local
1588 isEFLAGSLive(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const TargetRegisterInfo &TRI) argument
1876 saveEFLAGS( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc) argument
1894 restoreEFLAGS( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc, unsigned Reg) argument
1905 mergePredStateIntoSP( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc, unsigned PredStateReg) argument
1925 extractPredStateFromSP( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc) argument
1949 MachineBasicBlock &MBB = *MI.getParent(); local
2280 hardenValueInRegister( unsigned Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt, DebugLoc Loc) argument
2331 MachineBasicBlock &MBB = *MI.getParent(); local
2382 MachineBasicBlock &MBB = *MI.getParent(); local
2429 MachineBasicBlock &MBB = *MI.getParent(); local
[all...]
H A DX86FrameLowering.cpp145 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, argument
149 const MachineFunction *MF = MBB.getParent();
155 if (MBBI == MBB.end())
196 static bool isEAXLiveIn(MachineBasicBlock &MBB) { argument
197 for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
213 flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB) { argument
214 for (const MachineInstr &MI : MBB.terminators()) {
240 for (const MachineBasicBlock *Succ : MBB.successors())
249 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB, argument
266 if (isSub && !isEAXLiveIn(MBB))
2554 blockEndIsUnreachable(const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.cpp63 MachineBasicBlock &MBB = *MI.getParent(); local
64 MachineFunction &MF = *MBB.getParent();
69 for (auto &I : MBB)
90 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
110 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
112 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFixIrreducibleControlFlow.cpp78 for (auto *MBB : Blocks) {
79 if (MBB != Entry) {
80 for (auto *Pred : MBB->predecessors()) {
119 bool inRegion(MachineBasicBlock *MBB) const { return Blocks.count(MBB); }
131 for (auto *MBB : Blocks) {
132 for (auto *Succ : MBB->successors()) {
134 Reachable[MBB].insert(Succ);
135 WorkList.emplace_back(MBB, Succ);
141 MachineBasicBlock *MBB, *Suc local
209 auto *MBB = WorkList.pop_back_val(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DAsmPrinterHandler.h56 virtual void beginFragment(const MachineBasicBlock *MBB, argument
61 virtual void beginFunclet(const MachineBasicBlock &MBB, argument
H A DMachineInstrBundle.h27 void finalizeBundle(MachineBasicBlock &MBB,
34 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
36 MachineBasicBlock::instr_iterator finalizeBundle(MachineBasicBlock &MBB,
176 static MIBundleOperands end(const MachineBasicBlock &MBB) { argument
177 return {const_cast<MachineBasicBlock &>(MBB).instr_end(),
178 const_cast<MachineBasicBlock &>(MBB).instr_begin()->operands_end()};
198 static ConstMIBundleOperands end(const MachineBasicBlock &MBB) { argument
199 return {const_cast<MachineBasicBlock &>(MBB).instr_end(),
200 const_cast<MachineBasicBlock &>(MBB).instr_begin()->operands_end()};

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1234567891011>>