Searched refs:Inst (Results 76 - 100 of 412) sorted by relevance

1234567891011>>

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp85 void emitToStreamer(MCStreamer &S, const MCInst &Inst);
98 void emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
101 void emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
105 void emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
109 void emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
112 void emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
119 bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands);
125 bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
699 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
706 Inst
712 addRegOperands(MCInst &Inst, unsigned N) const argument
717 addImmOperands(MCInst &Inst, unsigned N) const argument
722 addFenceArgOperands(MCInst &Inst, unsigned N) const argument
741 addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const argument
757 addFRMArgOperands(MCInst &Inst, unsigned N) const argument
813 MCInst Inst; local
1634 emitToStreamer(MCStreamer &S, const MCInst &Inst) argument
1691 emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1705 emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1731 emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1746 emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) argument
1760 emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc, MCStreamer &Out, bool HasTmpReg) argument
1779 checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands) argument
1792 processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands, MCStreamer &Out) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DX86EVEX2VEXTablesEmitter.cpp177 for (const CodeGenInstruction *Inst : NumberedInstructions) {
179 if (!Inst->TheDef->isSubClassOf("X86Inst"))
184 if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
185 uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
187 VEXInsts[Opcode].push_back(Inst);
190 else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
191 !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
192 !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
193 !Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
194 !Inst
[all...]
H A DX86FoldTablesEmitter.cpp80 static bool isExplicitAlign(const CodeGenInstruction *Inst) { argument
81 return any_of(ExplicitAlign, [Inst](const char *InstStr) {
82 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
86 static bool isExplicitUnalign(const CodeGenInstruction *Inst) { argument
87 return any_of(ExplicitUnalign, [Inst](const char *InstStr) {
88 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
178 static bool hasRSTRegClass(const CodeGenInstruction *Inst) {
179 return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) {
185 static bool hasPtrTailcallRegClass(const CodeGenInstruction *Inst) {
186 return any_of(Inst
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp18 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} function in class:MipsAnalyzeImmediate::Inst
21 void MipsAnalyzeImmediate::AddInstr(InstSeqLs &SeqLs, const Inst &I) {
35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
41 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
48 AddInstr(SeqLs, Inst(SLL, Shamt));
61 AddInstr(SeqLs, Inst(ADDiu, MaskedImm));
/freebsd-11-stable/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DRegisterFileStatistics.cpp59 void RegisterFileStatistics::updateMoveElimInfo(const Instruction &Inst) { argument
60 if (!Inst.isOptimizableMove())
63 assert(Inst.getDefs().size() == 1 && "Expected a single definition!");
64 assert(Inst.getUses().size() == 1 && "Expected a single register use!");
65 const WriteState &WS = Inst.getDefs()[0];
66 const ReadState &RS = Inst.getUses()[0];
69 MoveElimInfo[Inst.getDefs()[0].getRegisterFileID()];
H A DRegisterFileStatistics.h68 void updateMoveElimInfo(const Instruction &Inst);
H A DInstructionInfoView.cpp40 const MCInst &Inst = Source[I]; local
41 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
49 SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID);
98 MCIP.printInst(&Inst, 0, "", STI, InstrStream);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp89 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); local
90 MAI->addInitialFrameState(Inst);
140 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
142 unsigned NumOps = Inst.getNumOperands();
145 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
151 Target = Region + Inst.getOperand(NumOps - 1).getImm();
156 Target = Addr + Inst.getOperand(NumOps - 1).getImm();
H A DMipsELFStreamer.cpp36 void MipsELFStreamer::EmitInstruction(const MCInst &Inst, argument
38 MCELFStreamer::EmitInstruction(Inst, STI);
43 for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) {
44 const MCOperand &Op = Inst.getOperand(OpIndex);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp121 bool needAlignInst(const MCInst &Inst) const;
148 void alignBranchesBegin(MCObjectStreamer &OS, const MCInst &Inst) override;
149 void alignBranchesEnd(MCObjectStreamer &OS, const MCInst &Inst) override;
167 bool mayNeedRelaxation(const MCInst &Inst,
174 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
181 static unsigned getRelaxedOpcodeBranch(const MCInst &Inst, bool is16BitMode) { argument
182 unsigned Op = Inst.getOpcode();
193 static unsigned getRelaxedOpcodeArith(const MCInst &Inst) { argument
194 unsigned Op = Inst.getOpcode();
278 static unsigned getRelaxedOpcode(const MCInst &Inst, boo argument
320 isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII) argument
416 alignBranchesBegin(MCObjectStreamer &OS, const MCInst &Inst) argument
458 alignBranchesEnd(MCObjectStreamer &OS, const MCInst &Inst) argument
586 mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const argument
616 relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, MCInst &Res) const argument
863 const MCCFIInstruction &Inst = Instrs[i]; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp389 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
392 Inst.addOperand(MCOperand::createImm(0));
394 Inst.addOperand(
397 Inst.addOperand(MCOperand::createExpr(Expr));
400 void addRegOperands(MCInst &Inst, unsigned N) const { argument
402 Inst.addOperand(MCOperand::createReg(getReg()));
405 void addImmOperands(MCInst &Inst, unsigned N) const { argument
407 addExpr(Inst, getImm());
410 void addBrTargetOperands(MCInst &Inst, unsigned N) const { argument
412 addExpr(Inst, getIm
415 addCallTargetOperands(MCInst &Inst, unsigned N) const argument
420 addCondCodeOperands(MCInst &Inst, unsigned N) const argument
425 addMemImmOperands(MCInst &Inst, unsigned N) const argument
431 addMemRegImmOperands(MCInst &Inst, unsigned N) const argument
439 addMemRegRegOperands(MCInst &Inst, unsigned N) const argument
447 addMemSplsOperands(MCInst &Inst, unsigned N) const argument
454 addImmShiftOperands(MCInst &Inst, unsigned N) const argument
459 addImm10Operands(MCInst &Inst, unsigned N) const argument
464 addLoImm16Operands(MCInst &Inst, unsigned N) const argument
488 addLoImm16AndOperands(MCInst &Inst, unsigned N) const argument
496 addHiImm16Operands(MCInst &Inst, unsigned N) const argument
519 addHiImm16AndOperands(MCInst &Inst, unsigned N) const argument
527 addLoImm21Operands(MCInst &Inst, unsigned N) const argument
655 MCInst Inst; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp69 const MCInst &Inst) const {
70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
77 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
112 const MCInst &Inst) const {
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
123 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/AsmParser/
H A DLLParser.h440 Instruction *Inst);
525 bool ParseInstructionMetadata(Instruction &Inst);
561 int ParseInstruction(Instruction *&Inst, BasicBlock *BB,
565 bool ParseRet(Instruction *&Inst, BasicBlock *BB, PerFunctionState &PFS);
566 bool ParseBr(Instruction *&Inst, PerFunctionState &PFS);
567 bool ParseSwitch(Instruction *&Inst, PerFunctionState &PFS);
568 bool ParseIndirectBr(Instruction *&Inst, PerFunctionState &PFS);
569 bool ParseInvoke(Instruction *&Inst, PerFunctionState &PFS);
570 bool ParseResume(Instruction *&Inst, PerFunctionState &PFS);
571 bool ParseCleanupRet(Instruction *&Inst, PerFunctionStat
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp165 /// Gets latency information for \p Inst from the itinerary
169 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) { argument
180 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
184 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
191 /// Gets latency information for \p Inst, based on \p DC information.
194 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) { argument
204 return getItineraryLatency(DC, Inst);
207 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
228 /// Emits latency information in DC->CommentStream for \p Inst, based
230 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) { argument
260 MCInst Inst; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopVersioningLICM.cpp394 for (auto &Inst : *Block) {
396 if (!instructionSafeForVersioning(&Inst)) {
398 return OptimizationRemarkMissed(DEBUG_TYPE, "IllegalLoopInst", &Inst)
548 for (auto &Inst : *Block) {
550 if (!Inst.mayReadFromMemory() && !Inst.mayWriteToMemory())
555 Inst.setMetadata(
557 MDNode::concatenate(Inst.getMetadata(LLVMContext::MD_noalias),
558 MDNode::get(Inst.getContext(), NoAliases)));
560 Inst
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/
H A DObjCARCOpts.cpp515 Instruction *Inst, ARCInstKind Class, const Value *Arg);
522 Instruction *Inst, const Value *&Arg, ARCInstKind Class,
528 bool VisitInstructionBottomUp(Instruction *Inst, BasicBlock *BB,
534 bool VisitInstructionTopDown(Instruction *Inst,
653 Instruction *Inst, const Value *&Arg, ARCInstKind Class,
656 assert(Inst->getParent() == AutoreleaseRV->getParent());
659 Arg = GetArgRCIdentityRoot(Inst);
676 << *AutoreleaseRV << "' paired with '" << *Inst << "'\n"); local
684 Inst->replaceAllUsesWith(cast<CallInst>(Inst)
651 OptimizeInlinedAutoreleaseRVCall( Function &F, DenseMap<BasicBlock *, ColorVector> &BlockColors, Instruction *Inst, const Value *&Arg, ARCInstKind Class, Instruction *AutoreleaseRV, const Value *&AutoreleaseRVArg) argument
835 Instruction *Inst = &*I++; local
880 OptimizeIndividualCallImpl( Function &F, DenseMap<BasicBlock *, ColorVector> &BlockColors, Instruction *Inst, ARCInstKind Class, const Value *Arg) argument
883 LLVM_DEBUG(dbgs() << "Visiting: Class: " << Class << "; " << *Inst << "\\n"); local
1317 VisitInstructionBottomUp( Instruction *Inst, BasicBlock *BB, BlotMapVector<Value *, RRInfo> &Retains, BBState &MyStates) argument
1418 Instruction *Inst = &*std::prev(I); local
1452 VisitInstructionTopDown(Instruction *Inst, DenseMap<Value *, RRInfo> &Releases, BBState &MyStates) argument
2011 Instruction *Inst = &*I++; local
2118 Instruction *Inst = &*I++; local
2338 Instruction *Inst = &*I++; local
[all...]
H A DPtrState.h183 void HandlePotentialUse(BasicBlock *BB, Instruction *Inst, const Value *Ptr,
185 bool HandlePotentialAlterRefCount(Instruction *Inst, const Value *Ptr,
201 void HandlePotentialUse(Instruction *Inst, const Value *Ptr,
204 bool HandlePotentialAlterRefCount(Instruction *Inst, const Value *Ptr,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULowerIntrinsics.cpp68 Instruction *Inst = cast<Instruction>(*I); local
73 auto *Memcpy = cast<MemCpyInst>(Inst);
86 auto *Memmove = cast<MemMoveInst>(Inst);
96 auto *Memset = cast<MemSetInst>(Inst);
H A DAMDGPUPerfHintAnalysis.cpp108 bool isIndirectAccess(const Instruction *Inst) const;
117 bool isLargeStride(const Instruction *Inst);
124 static const Value *getMemoryInstrPtr(const Instruction *Inst) { argument
125 if (auto LI = dyn_cast<LoadInst>(Inst)) {
128 if (auto SI = dyn_cast<StoreInst>(Inst)) {
131 if (auto AI = dyn_cast<AtomicCmpXchgInst>(Inst)) {
134 if (auto AI = dyn_cast<AtomicRMWInst>(Inst)) {
137 if (auto MI = dyn_cast<AnyMemIntrinsic>(Inst)) {
144 bool AMDGPUPerfHint::isIndirectAccess(const Instruction *Inst) const {
145 LLVM_DEBUG(dbgs() << "[isIndirectAccess] " << *Inst << '\
316 isLargeStride(const Instruction *Inst) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DIndirectCallPromotionAnalysis.h37 // current ValueDataArray and the given \p Inst.
38 uint32_t getProfitablePromotionCandidates(const Instruction *Inst,
H A DMemoryLocation.h204 static MemoryLocation get(const Instruction *Inst) { argument
205 return *MemoryLocation::getOrNone(Inst);
207 static Optional<MemoryLocation> getOrNone(const Instruction *Inst) { argument
208 switch (Inst->getOpcode()) {
210 return get(cast<LoadInst>(Inst));
212 return get(cast<StoreInst>(Inst));
214 return get(cast<VAArgInst>(Inst));
216 return get(cast<AtomicCmpXchgInst>(Inst));
218 return get(cast<AtomicRMWInst>(Inst));
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCAsmBackend.h56 virtual void alignBranchesBegin(MCObjectStreamer &OS, const MCInst &Inst) {} argument
57 virtual void alignBranchesEnd(MCObjectStreamer &OS, const MCInst &Inst) {} argument
141 /// \param Inst - The instruction to test.
144 virtual bool mayNeedRelaxation(const MCInst &Inst,
162 /// \param Inst The instruction to relax, which may be the same as the
166 virtual void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.cpp40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); local
41 MAI->addInitialFrameState(Inst);
50 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); local
51 MAI->addInitialFrameState(Inst);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVAsmPrinter.cpp54 void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
67 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { argument
69 bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
73 AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/IR/
H A DDiagnosticInfo.cpp241 const Instruction *Inst)
243 RemarkName, *Inst->getParent()->getParent(),
244 Inst->getDebugLoc(), Inst->getParent()) {}
275 const Instruction *Inst)
278 *Inst->getParent()->getParent(),
279 Inst->getDebugLoc(), Inst->getParent()) {}
296 const Instruction *Inst)
299 *Inst
239 OptimizationRemark(const char *PassName, StringRef RemarkName, const Instruction *Inst) argument
273 OptimizationRemarkMissed(const char *PassName, StringRef RemarkName, const Instruction *Inst) argument
294 OptimizationRemarkAnalysis(const char *PassName, StringRef RemarkName, const Instruction *Inst) argument
373 DiagnosticInfoMisExpect(const Instruction *Inst, Twine &Msg) argument
[all...]

Completed in 175 milliseconds

1234567891011>>