| /freebsd-11-stable/sys/dev/fe/ |
| H A D | if_fe.c | 565 #define LNX_CYCLE(D1,D2,D3,D4,K1,K2,K3,K4) \
566 (LNX_PH(D1,K1,0)|LNX_PH(D2,K2,8)|LNX_PH(D3,K3,16)|LNX_PH(D4,K4,24))
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| /freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/ExpressionParser/Clang/ |
| H A D | ClangASTSource.cpp | 877 template <class D2, template <class D> class TD, class D1>
878 TD<D2> DynCast(TD<D1> source) {
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenInsert.cpp | 793 unsigned D1 = std::distance(TB->begin(), ToI);
796 return D1+D2+D3;
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| H A D | HexagonBitTracker.cpp | 1254 static const unsigned Phys64[] = { D0, D1, D2 };
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| H A D | HexagonFrameLowering.cpp | 930 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
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| H A D | HexagonISelLowering.cpp | 276 .Case("r3:2", Hexagon::D1)
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 239 case D1:
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| H A D | HexagonMCDuplexInfo.cpp | 679 case Hexagon::D1:
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 81 SP::D0, SP::D16, SP::D1, SP::D17,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 149 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
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| /freebsd-11-stable/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | ClangAttrEmitter.cpp | 4112 [](const DocumentationData &D1, const DocumentationData &D2) {
4113 return D1.Heading < D2.Heading;
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 334 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2679 SDValue D1 = DAG.getSelectCC(DL, D0, SigSetHigh, One, Zero, ISD::SETNE); local
2680 D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 616 [](const decltype(NumOpsWantToKeepOrder)::value_type &D1,
618 return D1.second < D2.second;
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| /freebsd-11-stable/contrib/llvm-project/clang/include/clang/Sema/ |
| H A D | Sema.h | 6277 /// \param Result If no error occurred, receives the result of true if D1 is
6281 bool IsAtLeastAsConstrained(NamedDecl *D1, ArrayRef<const Expr *> AC1,
6285 /// If D1 was not at least as constrained as D2, but would've been if a pair
6289 bool MaybeEmitAmbiguousAtomicConstraintsDiagnostic(NamedDecl *D1,
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| /freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaChecking.cpp | 9993 if (const DeclRefExpr *D1 = dyn_cast_or_null<DeclRefExpr>(E1))
9995 return D1->getDecl() == D2->getDecl();
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| H A D | SemaDeclCXX.cpp | 11216 IsEquivalentForUsingDecl(ASTContext &Context, NamedDecl *D1, NamedDecl *D2) {
11217 if (D1->getCanonicalDecl() == D2->getCanonicalDecl())
11220 if (TypedefNameDecl *TD1 = dyn_cast<TypedefNameDecl>(D1))
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3015 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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| /freebsd-11-stable/contrib/amd/doc/ |
| H A D | texinfo.tex | 9293 \DeclareUnicodeCharacter{00D1}{\~N}
9461 \DeclareUnicodeCharacter{01D1}{\v{O}}
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1316 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3193 // D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context.
3232 case Mips::D1: return Mips::F3;
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