Searched refs:ADDC (Results 26 - 37 of 37) sorted by relevance
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 115 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1687 case HexagonISD::ADDC: return "HexagonISD::ADDC"; 2843 return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 3018 case PPC::ADDC: 3025 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
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H A D | PPCISelLowering.cpp | 207 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry. 210 setOperationAction(ISD::ADDC, VT, Legal); 15600 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1584 case ARMISD::ADDC: return "ARMISD::ADDC"; 4421 // We use ADDC here to correspond to its use in LowerUnsignedALUO. 4423 Value = DAG.getNode(ARMISD::ADDC, dl, 4531 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS); 11374 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by 11379 // loAdd -> ADDC | 11398 // Check that we are chained to the right ADDC or SUBC node. 11401 AddcSubcNode->getOpcode() != ARMISD::ADDC) || 11415 "Expect ADDC wit [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1514 case ISD::ADDC: return visitADDC(N); 2527 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0); 2687 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); 4699 APInt ADDC = ADDI->getAPIntValue(); local 4701 if (ADDC.getMinSignedBits() <= 64 && 4703 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 4707 ADDC |= Mask; 4708 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 4712 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
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H A D | TargetLowering.cpp | 5879 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) && 5882 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
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H A D | SelectionDAG.cpp | 3156 case ISD::ADDC: 3770 case ISD::ADDC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 260 setOperationAction(ISD::ADDC, VT, Expand);
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H A D | AMDGPUISelLowering.cpp | 325 // AMDGPU uses ADDC/SUBC/ADDE/SUBE 326 setOperationAction(ISD::ADDC, VT, Legal);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 335 setOperationAction(ISD::ADDC, MVT::i32, Custom); 339 setOperationAction(ISD::ADDC, MVT::i64, Custom); 2437 case ISD::ADDC: 3184 case ISD::ADDC:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 109 setOperationAction(ISD::ADDC, MVT::i32, Legal);
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