Searched refs:getReg (Results 151 - 175 of 244) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp171 assert(MO.getReg() != SP::O7 &&
174 MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg());
345 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
385 MI->getOperand(opNum+1).getReg() == SP::G0)
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp107 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp1584 unsigned CCReg = MI->getOperand(2).getReg();
1662 MI->getOperand(2).getReg() == ARM::PC &&
1707 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1714 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1814 unsigned Reg = CmpMI->getOperand(0).getReg();
1880 unsigned BaseReg = MI->getOperand(0).getReg();
1884 unsigned IdxReg = MI->getOperand(1).getReg();
1907 if (!MO.isReg() || !MO.getReg())
1909 if (MO.isDef() && MO.getReg() != BaseReg) {
1913 if (MO.isUse() && !MO.isKill() && MO.getReg() !
[all...]
H A DARMFrameLowering.cpp93 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
100 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
101 MI->getOperand(1).getReg() == ARM::SP)
175 unsigned Reg = CSI[i].getReg();
473 addReg(JumpTarget.getReg(), RegState::Kill);
600 unsigned Reg = CSI[i-1].getReg();
673 unsigned Reg = CSI[i-1].getReg();
751 unsigned DNum = CSI[i].getReg() - ARM::D8;
908 if (CSI[i].getReg() == ARM::D8) {
1432 unsigned PredReg = Old->getOperand(2).getReg();
[all...]
H A DThumb1RegisterInfo.cpp399 unsigned DestReg = MI.getOperand(0).getReg();
540 if (!MO.isReg() || MO.isUndef() || !MO.getReg() ||
541 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
543 if (MO.getReg() == ARM::R12) {
630 unsigned TmpReg = MI.getOperand(0).getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp122 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
124 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
136 unsigned SrcReg = MI->getOperand(1).getReg();
137 unsigned DstReg = MI->getOperand(0).getReg();
314 switch (MO.getReg()) {
617 unsigned Reg = CSI[I].getReg();
979 unsigned Reg = CSI[i].getReg();
1106 unsigned Reg = CSI[i].getReg();
1127 unsigned Reg = CSI[i].getReg();
1212 unsigned Reg = CSI[i].getReg();
[all...]
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp215 unsigned Reg = MO.getReg();
250 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
297 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
325 Uses.insert(PhysRegSUOper(SU, OperIdx, MO.getReg()));
329 unsigned Reg = MO.getReg();
367 unsigned Reg = MI->getOperand(OperIdx).getReg();
405 unsigned Reg = MI->getOperand(OperIdx).getReg();
777 unsigned Reg = MO.getReg();
H A DVirtRegMap.cpp306 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
308 unsigned VirtReg = MO.getReg();
H A DLiveIntervalAnalysis.cpp749 unsigned Reg = MO->getReg();
1018 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1019 TRI.hasRegUnit(MO->getReg(), Reg))
1077 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1078 !hasInterval(MOI->getReg())) {
1079 createAndComputeVirtRegInterval(MOI->getReg());
1116 if (!MO.isReg() || MO.getReg() != Reg)
H A DMachineBasicBlock.cpp361 if (I->getOperand(1).getReg() == PhysReg) {
362 unsigned VirtReg = I->getOperand(0).getReg();
725 if (!OI->isReg() || OI->getReg() == 0 ||
728 unsigned Reg = OI->getReg();
746 if (!OI->isReg() || OI->getReg() == 0)
749 unsigned Reg = OI->getReg();
856 unsigned Reg = MO.getReg();
H A DMachineTraceMetrics.cpp646 unsigned Reg = MO->getReg();
673 unsigned Reg = UseMI->getOperand(i).getReg();
709 unsigned Reg = MO->getReg();
741 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI);
886 unsigned Reg = MO->getReg();
914 unsigned Reg = MI->getOperand(ReadOps[i]).getReg();
964 unsigned Reg = DefMI->getOperand(DefOp).getReg();
H A DBranchFolding.cpp137 unsigned Reg = I->getOperand(0).getReg();
155 unsigned Reg = MO.getReg();
261 case MachineOperand::MO_Register: OperandHash = Op.getReg(); break;
1493 unsigned Reg = MO.getReg();
1525 unsigned Reg = MO.getReg();
1554 unsigned Reg = MO.getReg();
1639 unsigned Reg = MO.getReg();
1690 unsigned Reg = MO.getReg();
1702 unsigned Reg = MO.getReg();
H A DMachineVerifier.cpp853 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
859 const unsigned Reg = MO->getReg();
891 Reg != MI->getOperand(DefIdx).getReg())
988 const unsigned Reg = MO->getReg();
1235 unsigned Reg = BBI->getOperand(i).getReg();
1410 if (MOI->getReg() != Reg)
1413 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1414 !TRI->hasRegUnit(MOI->getReg(), Reg))
1529 if (!MOI->isReg() || MOI->getReg() != Reg)
H A DPrologEpilogInserter.cpp271 unsigned Reg = I->getReg();
335 EntryBlock->addLiveIn(CSI[i].getReg());
338 unsigned Reg = CSI[i].getReg();
366 unsigned Reg = CSI[i].getReg();
817 unsigned Reg = MO.getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp196 unsigned Reg = CSI[i-1].getReg();
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.cpp32 return MI.getOperand(OpNo).getReg() == R;
165 printRegName(O, Op.getReg());
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp117 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
640 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
771 if (II->getReg()) {
772 Reg = II->getReg();
780 assert(I->getReg() && "Unknown physical register!");
786 .addReg(I->getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp199 unsigned getReg() const { function in class:__anon2607::SparcOperand
236 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
249 Inst.addOperand(MCOperand::CreateReg(getReg()));
315 unsigned Reg = Op->getReg();
326 unsigned Reg = Op->getReg();
349 unsigned offsetReg = Op->getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp2655 MI->getOperand(0).getReg())
2706 .addReg(MI->getOperand(1).getReg())
2722 MI->getOperand(0).getReg())
2744 unsigned Fd = MI->getOperand(0).getReg();
2745 unsigned Ws = MI->getOperand(1).getReg();
2777 unsigned Fd = MI->getOperand(0).getReg();
2778 unsigned Ws = MI->getOperand(1).getReg();
2807 unsigned Wd = MI->getOperand(0).getReg();
2808 unsigned Wd_in = MI->getOperand(1).getReg();
2810 unsigned Fs = MI->getOperand(3).getReg();
[all...]
H A DMipsDelaySlotFiller.cpp276 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
358 if (MO.isReg() && MO.getReg())
359 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
/freebsd-10.2-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
173 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } function in class:__anon3859::RegUnitIterator
691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
703 CodeGenRegister *Reg = RegBank.getReg(Order.back());
762 if (contains(RegBank.getReg(Super.Orders[i][j])))
949 getReg(Regs[i]);
962 getReg((TupRegsCopy)[j]);
1034 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { function in class:CodeGenRegBank
1321 if (Reg != UnitI.getReg()) {
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp683 unsigned getReg() const { function in struct:__anon2641::X86Operand
874 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
875 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
888 Inst.addOperand(MCOperand::CreateReg(getReg()));
916 unsigned RegNo = getReg();
2130 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
2143 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
2172 unsigned reg = Op2->getReg();
2202 unsigned reg = Op1->getReg();
2345 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DR600ControlFlowFinalizer.cpp121 unsigned Reg = MO.getReg();
130 unsigned Reg = MO.getReg();
184 if (Srcs[i].first->getReg() != AMDGPU::ALU_LITERAL_X)
H A DR600ISelLowering.cpp143 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()))
158 MI->getOperand(0).getReg(),
159 MI->getOperand(1).getReg());
167 MI->getOperand(0).getReg(),
168 MI->getOperand(1).getReg());
176 MI->getOperand(0).getReg(),
177 MI->getOperand(1).getReg());
183 unsigned maskedRegister = MI->getOperand(0).getReg();
191 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
196 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp337 unsigned getReg() const { function in struct:__anon2554::PPCOperand
398 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
403 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
408 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
413 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
432 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
437 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
442 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));

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