Lines Matching refs:getReg
683 unsigned getReg() const {
874 (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
875 X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
888 Inst.addOperand(MCOperand::CreateReg(getReg()));
916 unsigned RegNo = getReg();
2130 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
2143 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
2172 unsigned reg = Op2->getReg();
2202 unsigned reg = Op1->getReg();
2345 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2346 !X86II::isX86_64ExtendedReg(Inst.getOperand(1).getReg()))
2370 if (X86II::isX86_64ExtendedReg(Inst.getOperand(0).getReg()) ||
2371 !X86II::isX86_64ExtendedReg(Inst.getOperand(2).getReg()))