Searched refs:getImm (Results 51 - 75 of 179) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.cpp170 O << Op.getImm();
182 O << (unsigned short int)MO.getImm();
191 O << (unsigned short int)(unsigned char)MO.getImm();
220 O << MipsFCCToString((Mips::CondCode)MO.getImm());
/freebsd-10.2-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp109 MI.getOperand(FIOperandNum + 1).getImm();
/freebsd-10.2-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.cpp138 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
139 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
153 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
154 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
H A DAMDGPUMCInstLower.cpp56 MCOp = MCOperand::CreateImm(MO.getImm());
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/
H A DSparcMCInstLower.cpp80 return MCOperand::CreateImm(MO.getImm());
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZMCInstLower.cpp83 return MCOperand::CreateImm(MO.getImm());
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.h108 (MO.getImm() == 1 || MO.getImm() == 2 ||
109 MO.getImm() == 4 || MO.getImm() == 8);
/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp52 return op.isImm() && op.getImm() == 0;
294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
303 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
399 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
H A DXCoreMCInstLower.cpp92 return MCOperand::CreateImm(MO.getImm() + offset);
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp507 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
634 unsigned ImmVal = (unsigned)MO.getImm();
664 unsigned Imm = MO.getImm();
698 .addImm(MI.getOperand(3).getImm()) // 'pred'
710 .addImm(MI.getOperand(3).getImm()) // 'pred'
721 .addImm(MI.getOperand(3).getImm())
722 .addImm(MI.getOperand(4).getImm()) // 'pred'
734 .addImm(MI.getOperand(4).getImm())
735 .addImm(MI.getOperand(5).getImm()) // 'pred'
747 .addImm(MI.getOperand(2).getImm())
[all...]
H A DThumb2InstrInfo.cpp82 unsigned Mask = MBBI->getOperand(1).getImm();
451 Offset += MI.getOperand(FrameRegIdx+1).getImm();
543 Offset += MI.getOperand(FrameRegIdx+1).getImm();
556 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
557 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
568 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
H A DARMBaseInstrInfo.cpp161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
416 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
432 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
443 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
450 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
460 .addImm(Pred[0].getImm())
468 PMO.setImm(Pred[0].getImm());
481 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
[all...]
H A DARMMCInstLower.cpp78 MCOp = MCOperand::CreateImm(MO.getImm());
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp263 unsigned getImm() const { function in class:__anon2502::CountValue
365 int64_t V = DI->getOperand(2).getImm();
562 EndV = EndValue->getImm();
570 InitV = InitialValue->getImm();
654 int64_t StartV = Start->getImm();
655 int64_t EndV = End->getImm();
726 StartV = Start->getImm();
728 EndV = End->getImm();
1094 int64_t CountImm = TripCount->getImm();
1206 return MO.getImm();
[all...]
H A DHexagonMCInstLower.cpp68 MCO = MCOperand::CreateImm(MO.getImm());
H A DHexagonExpandPredSpillCode.cpp92 int Offset = MI->getOperand(1).getImm();
139 int Offset = MI->getOperand(2).getImm();
/freebsd-10.2-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp238 uint64_t Amount = Old->getOperand(0).getImm();
253 uint64_t CalleeAmt = Old->getOperand(1).getImm();
272 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
H A DMSP430AsmPrinter.cpp75 O << MO.getImm();
H A DMSP430MCInstLower.cpp126 MCOp = MCOperand::CreateImm(MO.getImm());
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInst.cpp112 int ImmValue = MO.getImm();
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMips16RegisterInfo.cpp132 Offset += MI.getOperand(OpNo + 1).getImm();
H A DMipsISelDAGToDAG.h113 // getImm - Return a target constant with the specified value.
114 inline SDValue getImm(const SDNode *Node, uint64_t Imm) { function in class:llvm::MipsDAGToDAGISel
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp222 int64_t getImm() { return Imm + IC.execute(); } function in class:__anon2640::X86AsmParser::IntelExprStateMachine
688 const MCExpr *getImm() const { function in struct:__anon2641::X86Operand
724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
924 addExpr(Inst, getImm());
1387 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
1391 if (SM.getImm() || !Dis
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp58 if (MO.isImm() && MO.getImm() == 0) {
232 O << '#' << MO.getImm();
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp111 return static_cast<uint64_t>(MO.getImm());
171 Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx);

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