150397Sobrien//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===// 290075Sobrien// 318334Speter// The LLVM Compiler Infrastructure 450397Sobrien// 518334Speter// This file is distributed under the University of Illinois Open Source 618334Speter// License. See LICENSE.TXT for details. 718334Speter// 818334Speter//===----------------------------------------------------------------------===// 918334Speter// 1018334Speter// This file contains the XCore implementation of the TargetInstrInfo class. 1118334Speter// 1218334Speter//===----------------------------------------------------------------------===// 1318334Speter 1418334Speter#include "XCoreInstrInfo.h" 1518334Speter#include "XCore.h" 1618334Speter#include "XCoreMachineFunctionInfo.h" 1718334Speter#include "llvm/ADT/STLExtras.h" 1818334Speter#include "llvm/CodeGen/MachineFrameInfo.h" 1918334Speter#include "llvm/CodeGen/MachineInstrBuilder.h" 2018334Speter#include "llvm/MC/MCContext.h" 2118334Speter#include "llvm/Support/Debug.h" 2218334Speter#include "llvm/Support/ErrorHandling.h" 23117395Skan#include "llvm/Support/TargetRegistry.h" 2418334Speter 2518334Speter#define GET_INSTRINFO_CTOR_DTOR 2650397Sobrien#include "XCoreGenInstrInfo.inc" 27117395Skan 2818334Speternamespace llvm { 2918334Speternamespace XCore { 3018334Speter 3118334Speter // XCore Condition Codes 3218334Speter enum CondCode { 3318334Speter COND_TRUE, 3418334Speter COND_FALSE, 3518334Speter COND_INVALID 3618334Speter }; 3718334Speter} 3818334Speter} 3918334Speter 4018334Speterusing namespace llvm; 4118334Speter 4218334Speter 4350397Sobrien// Pin the vtable to this file. 4450397Sobrienvoid XCoreInstrInfo::anchor() {} 4518334Speter 46117395SkanXCoreInstrInfo::XCoreInstrInfo() 4718334Speter : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), 4818334Speter RI() { 4990075Sobrien} 5018334Speter 5118334Speterstatic bool isZeroImm(const MachineOperand &op) { 5250397Sobrien return op.isImm() && op.getImm() == 0; 5350397Sobrien} 5450397Sobrien 5518334Speter/// isLoadFromStackSlot - If the specified machine instruction is a direct 5690075Sobrien/// load from a stack slot, return the virtual or physical register number of 5790075Sobrien/// the destination along with the FrameIndex of the loaded stack slot. If 5890075Sobrien/// not, return 0. This predicate must return 0 if the instruction has 5990075Sobrien/// any side effects other than loading from the stack slot. 6090075Sobrienunsigned 6190075SobrienXCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ 6290075Sobrien int Opcode = MI->getOpcode(); 6390075Sobrien if (Opcode == XCore::LDWFI) 6490075Sobrien { 6518334Speter if ((MI->getOperand(1).isFI()) && // is a stack slot 6650397Sobrien (MI->getOperand(2).isImm()) && // the imm is zero 6750397Sobrien (isZeroImm(MI->getOperand(2)))) 6818334Speter { 6918334Speter FrameIndex = MI->getOperand(1).getIndex(); 7050397Sobrien return MI->getOperand(0).getReg(); 7118334Speter } 7218334Speter } 7318334Speter return 0; 7418334Speter} 7550397Sobrien 76117395Skan /// isStoreToStackSlot - If the specified machine instruction is a direct 7750397Sobrien /// store to a stack slot, return the virtual or physical register number of 7850397Sobrien /// the source reg along with the FrameIndex of the loaded stack slot. If 7950397Sobrien /// not, return 0. This predicate must return 0 if the instruction has 8050397Sobrien /// any side effects other than storing to the stack slot. 8190075Sobrienunsigned 8290075SobrienXCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 8390075Sobrien int &FrameIndex) const { 8450397Sobrien int Opcode = MI->getOpcode(); 8550397Sobrien if (Opcode == XCore::STWFI) 8650397Sobrien { 8750397Sobrien if ((MI->getOperand(1).isFI()) && // is a stack slot 88117395Skan (MI->getOperand(2).isImm()) && // the imm is zero 8950397Sobrien (isZeroImm(MI->getOperand(2)))) 9050397Sobrien { 9150397Sobrien FrameIndex = MI->getOperand(1).getIndex(); 9250397Sobrien return MI->getOperand(0).getReg(); 9350397Sobrien } 9450397Sobrien } 9550397Sobrien return 0; 96117395Skan} 97117395Skan 98117395Skan//===----------------------------------------------------------------------===// 9950397Sobrien// Branch Analysis 10050397Sobrien//===----------------------------------------------------------------------===// 10150397Sobrien 10250397Sobrienstatic inline bool IsBRU(unsigned BrOpc) { 10350397Sobrien return BrOpc == XCore::BRFU_u6 10450397Sobrien || BrOpc == XCore::BRFU_lu6 10550397Sobrien || BrOpc == XCore::BRBU_u6 10690075Sobrien || BrOpc == XCore::BRBU_lu6; 10790075Sobrien} 10890075Sobrien 10990075Sobrienstatic inline bool IsBRT(unsigned BrOpc) { 11090075Sobrien return BrOpc == XCore::BRFT_ru6 11190075Sobrien || BrOpc == XCore::BRFT_lru6 11290075Sobrien || BrOpc == XCore::BRBT_ru6 113117395Skan || BrOpc == XCore::BRBT_lru6; 114117395Skan} 115 116static inline bool IsBRF(unsigned BrOpc) { 117 return BrOpc == XCore::BRFF_ru6 118 || BrOpc == XCore::BRFF_lru6 119 || BrOpc == XCore::BRBF_ru6 120 || BrOpc == XCore::BRBF_lru6; 121} 122 123static inline bool IsCondBranch(unsigned BrOpc) { 124 return IsBRF(BrOpc) || IsBRT(BrOpc); 125} 126 127static inline bool IsBR_JT(unsigned BrOpc) { 128 return BrOpc == XCore::BR_JT 129 || BrOpc == XCore::BR_JT32; 130} 131 132/// GetCondFromBranchOpc - Return the XCore CC that matches 133/// the correspondent Branch instruction opcode. 134static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 135{ 136 if (IsBRT(BrOpc)) { 137 return XCore::COND_TRUE; 138 } else if (IsBRF(BrOpc)) { 139 return XCore::COND_FALSE; 140 } else { 141 return XCore::COND_INVALID; 142 } 143} 144 145/// GetCondBranchFromCond - Return the Branch instruction 146/// opcode that matches the cc. 147static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 148{ 149 switch (CC) { 150 default: llvm_unreachable("Illegal condition code!"); 151 case XCore::COND_TRUE : return XCore::BRFT_lru6; 152 case XCore::COND_FALSE : return XCore::BRFF_lru6; 153 } 154} 155 156/// GetOppositeBranchCondition - Return the inverse of the specified 157/// condition, e.g. turning COND_E to COND_NE. 158static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 159{ 160 switch (CC) { 161 default: llvm_unreachable("Illegal condition code!"); 162 case XCore::COND_TRUE : return XCore::COND_FALSE; 163 case XCore::COND_FALSE : return XCore::COND_TRUE; 164 } 165} 166 167/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 168/// true if it cannot be understood (e.g. it's a switch dispatch or isn't 169/// implemented for a target). Upon success, this returns false and returns 170/// with the following information in various cases: 171/// 172/// 1. If this block ends with no branches (it just falls through to its succ) 173/// just return false, leaving TBB/FBB null. 174/// 2. If this block ends with only an unconditional branch, it sets TBB to be 175/// the destination block. 176/// 3. If this block ends with an conditional branch and it falls through to 177/// an successor block, it sets TBB to be the branch destination block and a 178/// list of operands that evaluate the condition. These 179/// operands can be passed to other TargetInstrInfo methods to create new 180/// branches. 181/// 4. If this block ends with an conditional branch and an unconditional 182/// block, it returns the 'true' destination in TBB, the 'false' destination 183/// in FBB, and a list of operands that evaluate the condition. These 184/// operands can be passed to other TargetInstrInfo methods to create new 185/// branches. 186/// 187/// Note that RemoveBranch and InsertBranch must be implemented to support 188/// cases where this method returns success. 189/// 190bool 191XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 192 MachineBasicBlock *&FBB, 193 SmallVectorImpl<MachineOperand> &Cond, 194 bool AllowModify) const { 195 // If the block has no terminators, it just falls into the block after it. 196 MachineBasicBlock::iterator I = MBB.end(); 197 if (I == MBB.begin()) 198 return false; 199 --I; 200 while (I->isDebugValue()) { 201 if (I == MBB.begin()) 202 return false; 203 --I; 204 } 205 if (!isUnpredicatedTerminator(I)) 206 return false; 207 208 // Get the last instruction in the block. 209 MachineInstr *LastInst = I; 210 211 // If there is only one terminator instruction, process it. 212 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 213 if (IsBRU(LastInst->getOpcode())) { 214 TBB = LastInst->getOperand(0).getMBB(); 215 return false; 216 } 217 218 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 219 if (BranchCode == XCore::COND_INVALID) 220 return true; // Can't handle indirect branch. 221 222 // Conditional branch 223 // Block ends with fall-through condbranch. 224 225 TBB = LastInst->getOperand(1).getMBB(); 226 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 227 Cond.push_back(LastInst->getOperand(0)); 228 return false; 229 } 230 231 // Get the instruction before it if it's a terminator. 232 MachineInstr *SecondLastInst = I; 233 234 // If there are three terminators, we don't know what sort of block this is. 235 if (SecondLastInst && I != MBB.begin() && 236 isUnpredicatedTerminator(--I)) 237 return true; 238 239 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 240 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 241 242 // If the block ends with conditional branch followed by unconditional, 243 // handle it. 244 if (BranchCode != XCore::COND_INVALID 245 && IsBRU(LastInst->getOpcode())) { 246 247 TBB = SecondLastInst->getOperand(1).getMBB(); 248 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 249 Cond.push_back(SecondLastInst->getOperand(0)); 250 251 FBB = LastInst->getOperand(0).getMBB(); 252 return false; 253 } 254 255 // If the block ends with two unconditional branches, handle it. The second 256 // one is not executed, so remove it. 257 if (IsBRU(SecondLastInst->getOpcode()) && 258 IsBRU(LastInst->getOpcode())) { 259 TBB = SecondLastInst->getOperand(0).getMBB(); 260 I = LastInst; 261 if (AllowModify) 262 I->eraseFromParent(); 263 return false; 264 } 265 266 // Likewise if it ends with a branch table followed by an unconditional branch. 267 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { 268 I = LastInst; 269 if (AllowModify) 270 I->eraseFromParent(); 271 return true; 272 } 273 274 // Otherwise, can't handle this. 275 return true; 276} 277 278unsigned 279XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 280 MachineBasicBlock *FBB, 281 const SmallVectorImpl<MachineOperand> &Cond, 282 DebugLoc DL)const{ 283 // Shouldn't be a fall through. 284 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 285 assert((Cond.size() == 2 || Cond.size() == 0) && 286 "Unexpected number of components!"); 287 288 if (FBB == 0) { // One way branch. 289 if (Cond.empty()) { 290 // Unconditional branch 291 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); 292 } else { 293 // Conditional branch. 294 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 295 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 296 .addMBB(TBB); 297 } 298 return 1; 299 } 300 301 // Two-way Conditional branch. 302 assert(Cond.size() == 2 && "Unexpected number of components!"); 303 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 304 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 305 .addMBB(TBB); 306 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); 307 return 2; 308} 309 310unsigned 311XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 312 MachineBasicBlock::iterator I = MBB.end(); 313 if (I == MBB.begin()) return 0; 314 --I; 315 while (I->isDebugValue()) { 316 if (I == MBB.begin()) 317 return 0; 318 --I; 319 } 320 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) 321 return 0; 322 323 // Remove the branch. 324 I->eraseFromParent(); 325 326 I = MBB.end(); 327 328 if (I == MBB.begin()) return 1; 329 --I; 330 if (!IsCondBranch(I->getOpcode())) 331 return 1; 332 333 // Remove the branch. 334 I->eraseFromParent(); 335 return 2; 336} 337 338void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 339 MachineBasicBlock::iterator I, DebugLoc DL, 340 unsigned DestReg, unsigned SrcReg, 341 bool KillSrc) const { 342 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); 343 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); 344 345 if (GRDest && GRSrc) { 346 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 347 .addReg(SrcReg, getKillRegState(KillSrc)) 348 .addImm(0); 349 return; 350 } 351 352 if (GRDest && SrcReg == XCore::SP) { 353 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); 354 return; 355 } 356 357 if (DestReg == XCore::SP && GRSrc) { 358 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) 359 .addReg(SrcReg, getKillRegState(KillSrc)); 360 return; 361 } 362 llvm_unreachable("Impossible reg-to-reg copy"); 363} 364 365void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator I, 367 unsigned SrcReg, bool isKill, 368 int FrameIndex, 369 const TargetRegisterClass *RC, 370 const TargetRegisterInfo *TRI) const 371{ 372 DebugLoc DL; 373 if (I != MBB.end()) DL = I->getDebugLoc(); 374 BuildMI(MBB, I, DL, get(XCore::STWFI)) 375 .addReg(SrcReg, getKillRegState(isKill)) 376 .addFrameIndex(FrameIndex) 377 .addImm(0); 378} 379 380void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 381 MachineBasicBlock::iterator I, 382 unsigned DestReg, int FrameIndex, 383 const TargetRegisterClass *RC, 384 const TargetRegisterInfo *TRI) const 385{ 386 DebugLoc DL; 387 if (I != MBB.end()) DL = I->getDebugLoc(); 388 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 389 .addFrameIndex(FrameIndex) 390 .addImm(0); 391} 392 393/// ReverseBranchCondition - Return the inverse opcode of the 394/// specified Branch instruction. 395bool XCoreInstrInfo:: 396ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 397 assert((Cond.size() == 2) && 398 "Invalid XCore branch condition!"); 399 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); 400 return false; 401} 402