/freebsd-10.1-release/contrib/llvm/lib/Target/R600/ |
H A D | R600OptimizeVectorRegisters.cpp | 86 const R600InstrInfo *TII; member in class:__anon2575::R600VectorRegMerger 110 TII(0) { } 132 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 194 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG), 211 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg) 248 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) 316 TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo()); 329 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
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H A D | SIRegisterInfo.cpp | 31 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(TM.getInstrInfo()); local 32 TII->reserveIndirectRegisters(Reserved, MF);
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H A D | SIISelLowering.cpp | 345 const SIInstrInfo *TII = local 353 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo) 355 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo) 357 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi) 359 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi) 364 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg) 373 const SIInstrInfo *TII = local 375 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), 389 const SIInstrInfo *TII = local 393 BuildMI(*BB, I, MI->getDebugLoc(), TII 941 const SIInstrInfo *TII = local 976 const SIInstrInfo *TII = local 1085 const SIInstrInfo *TII = local 1317 const SIInstrInfo *TII = local 1331 const SIInstrInfo *TII = local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 133 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 222 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 296 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 334 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 338 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 458 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 498 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 508 TII [all...] |
H A D | FastISel.cpp | 233 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 576 TII.get(TargetOpcode::INLINEASM)) 647 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0, 651 TII.get(TargetOpcode::DBG_VALUE)) 665 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 801 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 883 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 1100 TII(*TM.getInstrInfo()), 1210 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1220 const MCInstrDesc &II = TII [all...] |
H A D | ScheduleDAGRRList.cpp | 276 const TargetInstrInfo *TII, 306 const MCInstrDesc Desc = TII->get(Opcode); 307 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 408 const TargetInstrInfo *TII) { 418 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII)) 425 (unsigned)TII->getCallFrameDestroyOpcode()) { 428 (unsigned)TII->getCallFrameSetupOpcode()) { 458 const TargetInstrInfo *TII) { 470 MyNestLevel, MyMaxNest, TII)) 483 (unsigned)TII 274 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument 406 IsChainDependent(SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII) argument 457 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII) argument 1190 getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) argument [all...] |
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
H A D | EarlyIfConversion.cpp | 81 const TargetInstrInfo *TII; member in class:__anon2235::SSAIfConv 155 TII = MF.getTarget().getInstrInfo(); 222 if (!I->isSafeToMove(TII, 0, DontMoveAcrossStore)) { 388 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) { 422 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg, 463 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 484 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 540 TII->RemoveBranch(*Head); 567 TII->InsertBranch(*Head, Tail, 0, EmptyCond, HeadDL); 580 const TargetInstrInfo *TII; member in class:__anon2236::EarlyIfConverter [all...] |
H A D | PeepholeOptimizer.cpp | 103 const TargetInstrInfo *TII; member in class:__anon2280::PeepholeOptimizer 161 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 295 TII->get(TargetOpcode::COPY), NewVR) 321 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || 327 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { 341 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable)) 345 if (!TII->optimizeSelect(MI)) 485 TII->get(TargetOpcode::COPY), NewVR) 555 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) { 571 TII [all...] |
H A D | CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII; member in class:llvm::CriticalAntiDepBreaker
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H A D | TwoAddressInstructionPass.cpp | 71 const TargetInstrInfo *TII; member in class:__anon2326::TwoAddressInstructionPass 187 if (!MI->isSafeToMove(TII, AA, SeenStore)) 339 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, argument 404 const TargetInstrInfo *TII, 427 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 454 const TargetInstrInfo *TII, 465 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 579 MachineInstr *NewMI = TII->commuteInstruction(MI); 627 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV); 668 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCop 402 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument 452 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument [all...] |
H A D | ExecutionDepsFix.cpp | 132 const TargetInstrInfo *TII; member in class:__anon2240::ExeDepsFix 310 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain); 451 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI); 499 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI); 525 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI); 527 TII->breakPartialRegDependency(MI, i, TRI); 565 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI); 638 TII->setExecutionDomain(mi, domain); 717 TII = MF->getTarget().getInstrInfo();
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H A D | TailDuplication.cpp | 62 const TargetInstrInfo *TII; member in class:__anon2325::TailDuplicatePass 131 TII = MF.getTarget().getInstrInfo(); 422 MachineInstr *NewMI = TII->duplicate(MI, MF); 650 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 681 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 719 TII->RemoveBranch(*PredBB); 722 TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc()); 769 if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) 783 TII->RemoveBranch(*PredBB); 824 TII [all...] |
H A D | LiveRangeEdit.cpp | 55 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 154 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); 202 if (!DefMI->isSafeToMove(&TII, 0, SawStore)) 212 MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI); 241 if (!MI->isSafeToMove(&TII, 0, SawStore)) { 304 MI->setDesc(TII.get(TargetOpcode::KILL));
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H A D | CalcSpillWeights.cpp | 77 const TargetInstrInfo &TII) { 89 if (!TII.isTriviallyReMaterializable(MI, LIS.getAliasAnalysis())) 75 isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const TargetInstrInfo &TII) argument
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H A D | DFAPacketizer.cpp | 131 TII = TM.getInstrInfo(); 132 ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
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H A D | OptimizePHIs.cpp | 32 const TargetInstrInfo *TII; member in class:__anon2278::OptimizePHIs 65 TII = Fn.getTarget().getInstrInfo();
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/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonVLIWPacketizer.cpp | 193 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo(); local 241 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn)) 275 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 291 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 305 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 325 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 405 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 413 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 436 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; 449 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 232 DL, TII.get(Opc), ResultReg), AM); 252 TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1); 292 DL, TII.get(Opc)), AM).addReg(ValReg); 321 DL, TII.get(Opc)), AM) 431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg); 867 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 884 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 891 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET)); 971 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc)) 983 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII [all...] |
/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineSSAUpdater.h | 54 const TargetInstrInfo *TII; member in class:llvm::MachineSSAUpdater
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H A D | LiveRangeEdit.h | 65 const TargetInstrInfo &TII; member in class:llvm::LiveRangeEdit 122 TII(*MF.getTarget().getInstrInfo()),
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/freebsd-10.1-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 134 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); local 136 MI.setDesc(TII.get(MSP430::MOV16rr)); 145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
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/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 622 const AArch64InstrInfo &TII) { 633 DebugLoc dl, const TargetInstrInfo &TII, 643 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg) 649 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg) 657 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg) 665 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg) 673 BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg) 699 BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg) 709 BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg) 717 DebugLoc dl, const TargetInstrInfo &TII, 620 rewriteA64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo &TII) argument 631 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc dl, const TargetInstrInfo &TII, unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, int64_t NumBytes, MachineInstr::MIFlag MIFlags) argument 716 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, const TargetInstrInfo &TII, unsigned ScratchReg, int64_t NumBytes, MachineInstr::MIFlag MIFlags) argument 788 const AArch64InstrInfo *TII = TM->getInstrInfo(); local 809 const AArch64InstrInfo *TII = TM->getInstrInfo(); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsConstantIslandPass.cpp | 241 const Mips16InstrInfo *TII; member in class:__anon2519::MipsConstantIslands 363 TII = (const Mips16InstrInfo*)MF->getTarget().getInstrInfo(); 485 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY)) 678 BBI.Size += TII->GetInstSizeInBytes(I); 696 Offset += TII->GetInstSizeInBytes(I); 752 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB); 1000 UserMI->setDesc(TII->get(U.getLongFormOpcode())); 1131 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); 1175 for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI); 1177 Offset += TII [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 61 const ARMBaseInstrInfo *TII; member in struct:__anon2435::A15SDOptimizer 441 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), 460 TII->get(TargetOpcode::COPY), Out) 476 TII->get(TargetOpcode::REG_SEQUENCE), Out) 495 TII->get(ARM::VEXTd32), Out) 511 TII->get(TargetOpcode::INSERT_SUBREG), Out) 527 TII->get(TargetOpcode::IMPLICIT_DEF), Out); 686 TII = static_cast<const ARMBaseInstrInfo*>(Fn.getTarget().getInstrInfo());
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/freebsd-10.1-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 132 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local 176 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); 204 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(), 221 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); local 230 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(), 246 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG)); 288 const TargetInstrInfo *TII) { 304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg) 284 emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII) argument
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