Lines Matching refs:TII
345 const SIInstrInfo *TII =
353 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
355 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
357 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
359 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
364 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
373 const SIInstrInfo *TII =
375 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
389 const SIInstrInfo *TII =
393 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
941 const SIInstrInfo *TII =
943 if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
976 const SIInstrInfo *TII =
978 const SIRegisterInfo &TRI = TII->getRegisterInfo();
993 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1085 const SIInstrInfo *TII =
1087 const MCInstrDesc *Desc = &TII->get(Opcode);
1093 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1094 const MCInstrDesc *DescRev = OpcodeRev == -1 ? 0 : &TII->get(OpcodeRev);
1101 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
1317 const SIInstrInfo *TII =
1321 if (TII->isMIMG(Node->getMachineOpcode()))
1331 const SIInstrInfo *TII =
1333 if (!TII->isMIMG(MI->getOpcode()))
1350 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1351 MI->setDesc(TII->get(NewOpcode));