/freebsd-10.1-release/contrib/binutils/opcodes/ |
H A D | i386-opc.h | 36 set if Reg --> Regmem; 37 unset if Regmem --> Reg. */ 138 'operand_types[i] = Reg|Imm' specifies that operand i can be 192 #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */ macro
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/freebsd-10.1-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | LiveRangeEdit.h | 209 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 211 void eraseVirtReg(unsigned Reg);
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H A D | SelectionDAG.h | 475 SDValue getRegister(unsigned Reg, EVT VT); 487 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) { argument 489 getRegister(Reg, N.getValueType()), N); 495 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N, argument 498 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue }; 502 // Similar to last getCopyToReg() except parameter Reg is a SDValue 503 SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N, argument 506 SDValue Ops[] = { Chain, Reg, N, Glue }; 510 SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) { argument 512 SDValue Ops[] = { Chain, getRegister(Reg, V 519 getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT, SDValue Glue) argument [all...] |
H A D | LiveInterval.h | 535 LiveInterval(unsigned Reg, float Weight) argument 536 : reg(Reg), weight(Weight) {}
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H A D | FastISel.h | 342 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
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/freebsd-10.1-release/contrib/llvm/lib/CodeGen/ |
H A D | ExecutionDepsFix.cpp | 171 int regIndex(unsigned Reg); 204 int ExeDepsFix::regIndex(unsigned Reg) { argument 205 assert(Reg < AliasMap.size() && "Invalid register"); 206 return AliasMap[Reg];
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/freebsd-10.1-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 156 unsigned Reg, MachineRegisterInfo *MRI) const;
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H A D | PPCFastISel.cpp | 70 unsigned Reg; member in union:__anon2546::Address::__anon2548 79 Base.Reg = 0; 384 if (Addr.Base.Reg == 0) 385 Addr.Base.Reg = getRegForValue(Obj); 389 if (Addr.Base.Reg != 0) 390 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); 392 return Addr.Base.Reg != 0; 412 Addr.Base.Reg = ResultReg; 509 .addImm(Addr.Offset).addReg(Addr.Base.Reg); 533 .addReg(Addr.Base.Reg) 1536 unsigned Reg = getRegForValue(RV); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DwarfCompileUnit.h | 273 void addRegisterOp(DIEBlock *TheDie, unsigned Reg); 276 void addRegisterOffset(DIEBlock *TheDie, unsigned Reg, int64_t Offset);
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/freebsd-10.1-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 60 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 71 if (unsigned Reg = State.AllocateReg(RegList, 6)) 72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 92 unsigned Reg = 0; local 96 Reg = SP::I0 + Offset/8; 99 Reg = SP::D0 + Offset/8; 102 Reg = SP::F1 + Offset/4; 105 Reg = SP::Q0 + Offset/16; 108 if (Reg) { 141 unsigned Reg = SP::I0 + Offset/8; local 163 toCallerWindow(unsigned Reg) argument 221 unsigned Reg = SFI->getSRetReturnReg(); local 483 unsigned Reg = SFI->getSRetReturnReg(); local 887 unsigned Reg = toCallerWindow(RegsToPass[i].first); local 1272 unsigned Reg = toCallerWindow(VA.getLocReg()); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.c | 1186 insn->reg = (Reg)(insn->regBase + reg); 1371 insn->vvvv = (Reg)fixupRegValue(insn, 1379 insn->reg = (Reg)fixupRegValue(insn, 1456 insn->opcodeRegister = (Reg)(MODRM_REG_AL + ((bFromREX(insn->rexPrefix) << 3) 1461 insn->opcodeRegister = (Reg)(MODRM_REG_SPL 1467 insn->opcodeRegister = (Reg)(MODRM_REG_AX 1472 insn->opcodeRegister = (Reg)(MODRM_REG_EAX 1477 insn->opcodeRegister = (Reg)(MODRM_REG_RAX
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/freebsd-10.1-release/contrib/llvm/tools/llvm-objdump/ |
H A D | COFFDump.cpp | 50 static StringRef getUnwindRegisterName(uint8_t Reg) { argument 51 switch(Reg) {
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/freebsd-10.1-release/contrib/llvm/utils/TableGen/ |
H A D | AsmWriterEmitter.cpp | 527 const CodeGenRegister &Reg = *Registers[i]; 533 AsmName = Reg.TheDef->getValueAsString("AsmName"); 535 AsmName = Reg.getName(); 539 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 549 Reg.TheDef->getValueAsListOfStrings("AltNames"); 551 PrintFatalError(Reg.TheDef->getLoc(),
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H A D | DAGISelMatcher.h | 848 /// Reg - The def for the register that we're emitting. If this is null, then 850 const CodeGenRegister *Reg; member in class:llvm::EmitRegisterMatcher 854 : Matcher(EmitRegister), Reg(reg), VT(vt) {} 856 const CodeGenRegister *getReg() const { return Reg; } 866 return cast<EmitRegisterMatcher>(M)->Reg == Reg && 870 return ((unsigned)(intptr_t)Reg) << 4 | VT;
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H A D | DAGISelMatcherEmitter.cpp | 448 const CodeGenRegister *Reg = Matcher->getReg(); local 451 if (Reg && Reg->EnumValue > 255) { 453 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n"; 457 if (Reg) { 458 OS << getQualifiedName(Reg->TheDef) << ",\n";
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H A D | DAGISelMatcher.cpp | 224 if (Reg) 225 OS << Reg->getName();
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/freebsd-10.1-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 189 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 190 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 203 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 204 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 214 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { 215 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 260 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { 261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 275 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 276 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocV 719 unsigned Reg = local 996 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 96 void setBaseReg(SDValue Reg) { argument 98 Base_Reg = Reg; 1098 SDValue Reg; local 1105 Reg = MulVal.getNode()->getOperand(0); 1110 Reg = N.getNode()->getOperand(0); 1112 Reg = N.getNode()->getOperand(0); 1115 AM.IndexReg = AM.Base_Reg = Reg; 2609 SDValue Reg = N0.getNode()->getOperand(0); local 2620 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2621 Reg 2645 SDValue Reg = N0.getNode()->getOperand(0); local 2681 SDValue Reg = N0.getNode()->getOperand(0); local 2703 SDValue Reg = N0.getNode()->getOperand(0); local [all...] |
/freebsd-10.1-release/contrib/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 220 struct RegOp Reg; member in union:__anon2426::AArch64Operand::__anon2427 247 return Reg.RegNum; 862 Op->Reg.RegNum = RegNum; 868 Op->Reg.RegNum = RegNum; 1998 unsigned Reg, Count = 1; local 2001 if (!TryParseVector(Reg, RegEndLoc, LayoutStr, LayoutLoc)) 2014 unsigned Space = (Reg < Reg2) ? (Reg2 - Reg) : (Reg2 + 32 - Reg); 2027 unsigned LastReg = Reg; [all...] |
/freebsd-10.1-release/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ProgramState.h | 337 bool isTainted(const MemRegion *Reg, TaintTagType Kind=TaintTagGeneric) const; 340 DynamicTypeInfo getDynamicTypeInfo(const MemRegion *Reg) const; 343 ProgramStateRef setDynamicTypeInfo(const MemRegion *Reg, 347 ProgramStateRef setDynamicTypeInfo(const MemRegion *Reg, argument 350 return setDynamicTypeInfo(Reg, DynamicTypeInfo(NewTy, CanBeSubClassed));
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/freebsd-10.1-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 288 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) { argument 289 if (!LiveOutRegInfo.inBounds(Reg)) 292 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
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/freebsd-10.1-release/sys/contrib/dev/acpica/include/ |
H A D | acmacros.h | 278 #define ACPI_REGISTER_INSERT_VALUE(Reg, Pos, Mask, Val) \ 279 Reg = (Reg & (~(Mask))) | ACPI_REGISTER_PREPARE_BITS(Val, Pos, Mask)
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H A D | acpixf.h | 682 ACPI_GENERIC_ADDRESS *Reg); 687 ACPI_GENERIC_ADDRESS *Reg);
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/freebsd-10.1-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 582 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 786 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 788 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 793 unsigned Reg, MachineRegisterInfo *MRI) const { 859 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 872 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 581 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 792 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
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/freebsd-10.1-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.h | 197 unsigned encodeVirtualRegister(unsigned Reg);
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