Lines Matching refs:Reg

60   if (unsigned Reg = State.AllocateReg(RegList, 6)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
71 if (unsigned Reg = State.AllocateReg(RegList, 6))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
92 unsigned Reg = 0;
96 Reg = SP::I0 + Offset/8;
99 Reg = SP::D0 + Offset/8;
102 Reg = SP::F1 + Offset/4;
105 Reg = SP::Q0 + Offset/16;
108 if (Reg) {
109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
141 unsigned Reg = SP::I0 + Offset/8;
147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
163 static unsigned toCallerWindow(unsigned Reg) {
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
167 return Reg;
221 unsigned Reg = SFI->getSRetReturnReg();
222 if (!Reg)
224 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
483 unsigned Reg = SFI->getSRetReturnReg();
484 if (!Reg) {
485 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
486 SFI->setSRetReturnReg(Reg);
488 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
887 unsigned Reg = toCallerWindow(RegsToPass[i].first);
888 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
1143 // Load into Reg and Reg+1
1272 unsigned Reg = toCallerWindow(VA.getLocReg());
1279 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1284 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);