/broadcom-cfe-1.4.2/cfe/arch/mips/common/src/ |
H A D | dev_flash_all.S | 178 and t1,t2,0x80 # done if bit7 of flash 180 beq t1,t0,2f 182 and t1,t2,0x20 # not done if bit5 183 bne t1,0x20,1b # is still set
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H A D | init_mips.S | 616 lw t1,4(v0) 624 sw t1,4(s0) 746 lw t1,R_REL_INFO(v0) # Get symbol type 748 andi t2,t1,M_REL_TYPE # Ignore R_MIPS_NONE 765 srl t1,S_REL_SYM # Symbol "info" is index 766 sll t1,4 # back to symtab index 767 add t1,t1,REG_SYMTAB # t1 points at symtab entry 769 lw t2,R_ELF32SYM_ST_VALUE(t1) # Symbo [all...] |
H A D | zipstart_entry.S | 132 SREG t1,XGR_T1(k1) 158 mfc0 t1,C0_SR 165 SREG t1,XCP0_SR(k1) 185 LREG t1,XGR_HI(k1) 187 mthi t1 195 LREG t1,XGR_T1(k1)
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H A D | zipstart_init.S | 410 LR t1,R_SEG_ETEXT(a0) 412 add t1,t0 414 and t1,t0 # t1 = _etext rounded up to 16-byte boundary 419 1: LR t4,0(t1) # read one cache line 420 LR t5,(REGSIZE*1)(t1) 421 LR t6,(REGSIZE*2)(t1) 422 LR t7,(REGSIZE*3)(t1) 427 add t1,(REGSIZE*4) 461 LR t1,R_SEG_FTEX [all...] |
H A D | init_ram.S | 241 li t1,K0BASE # write into both cached 247 SR t3,CFE_LOCORE_GLOBAL_CPUEPT(t1) 251 SR t3,CFE_LOCORE_GLOBAL_APIEPT(t1) 348 LR t1,R_SEG_FTEXT(a0) 350 sub t0,t0,t1 352 SR t1,mem_textbase
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H A D | dev_flashop_engine.S | 239 xori t1,reg_src,0x3 240 lbu t0,0(t1) 261 xori t1,reg_src,0x2 262 lhu t0,0(t1) 283 xori t1,reg_src,0x3 284 lbu t0,0(t1) 427 and t1,t2,0x80 # done if bit7 of flash 429 beq t1,t0,2f 431 and t1,t2,0x20 # not done if bit5 432 bne t1, [all...] |
H A D | apientry.S | 218 SPIN_LOCK(cfe_spinlock,t0,t1)
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/broadcom-cfe-1.4.2/cfe/verif/ |
H A D | vapi.S | 133 sd t1,SAVE_T1(k0) ; \ 150 ld t1,SAVE_T1(k0) ; \ 334 dli t1,CHIP_CPU_RESET # Reset mask 335 and t0,t1 # Test if CPU is in reset 601 add t1,RECPTR,VAPI_REC_DATA # a1 = ptr to data ara 603 sd a1,0(t1) 604 add t1,8 610 sd t0,0(t1) 612 add t1,8 656 mfc0 t1,C0_PRI [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcm1480/src/ |
H A D | bcm1480_l2cache.S | 80 * t0,t1,t2 106 or t1,t2,M_SR_KX 107 mtc0 t1,C0_SR 121 li t1,16 123 li t1,BCM1480_L2C_ENTRIES_PER_WAY*BCM1480_L2C_NUM_WAYS 136 subu t1,4 137 bne t1,0,1b 177 * t0,t1 235 * t0,t1 289 * t0,t1,t [all...] |
H A D | bcm1480_ircpoll.S | 270 li t1,M_SR_IMMASK /* Mask all interrupt levels */ 271 nor t1,t1,zero 272 and t0,t0,t1 307 li t1,M_SR_IMMASK|M_SR_IE 309 and v0,t0,t1 /* current mask bits */ 343 li t1,M_SR_IMMASK|M_SR_IE 345 and a0,a0,t1
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H A D | sb1_cpuinit.S | 92 move t1,zero 257 li t1,(K_NTLBENTRIES-1) /* index */ 262 mtc0 t1,C0_INX 265 bnez t1,1b 266 subu t1,1 # BDSLOT
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H A D | bcm1480_cpu.S | 136 ld t1,0(t0) 138 and t1,t1,t2 139 BCM1480_WRITE_SYSTEM_CFG(t0, t1)
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/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/sb1250/src/ |
H A D | sb1250_ircpoll.S | 272 li t1,M_SR_IMMASK /* Mask all interrupt levels */ 273 nor t1,t1,zero 274 and t0,t0,t1 309 li t1,M_SR_IMMASK|M_SR_IE 311 and v0,t0,t1 /* current mask bits */ 345 li t1,M_SR_IMMASK|M_SR_IE 347 and a0,a0,t1
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H A D | sb1_cpuinit.S | 93 move t1,zero 256 li t1,(K_NTLBENTRIES-1) /* index */ 261 mtc0 t1,C0_INX 264 bnez t1,1b 265 subu t1,1 # BDSLOT 295 mfc0 t1, $23, 2 # get the original value of defeature reg 296 or t1, t0, t1 297 mtc0 t1, $23, 2
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H A D | sb1250_cpu.S | 137 ld t1,0(t0) 139 and t1,t1,t2 140 sd t1,0(t0)
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H A D | diag_l2cache.S | 280 move t1, zero 281 sd t1, 0(t0) 295 and t1,t0,(0xF0FF << S_SYS_PART) /* ignore CPU count */ 297 bne t2,t1,2f /* go if not a sb1x50 */ 300 and t1,t0,M_SYS_REVISION 302 bge t1,t2,3f /* run diags if >= pass3 (0x20) */ 305 bge t1,t2,1f /* go if pass2 or better (>= 0x03) */ 310 1: dsrl t1,t0,S_SYS_WID /* Get Wafer ID register */ 311 bne t1,zero,2b /* leave if register is set (no diags) */ 345 or t1,t [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/bcmsb/src/ |
H A D | sbmemc.S | 92 * t1: - - mode 148 lw t1,R_SBIDHIGH(t0) 149 and t1,t1,M_SBID_CR 150 srl t1,t1,S_SBID_CR 151 bne t1,K_CR_CHIP_COMMON,notcc 170 lw t1, 0(a2) 171 beq t0,t1,read_parms 180 lw t1, [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/src/ |
H A D | sb1250_memcpy.S | 139 and t1, dst, ADDRMASK 147 bnez t1, dst_unaligned 168 LOAD t1, FIRST(1)(src) 192 STORE t1, FIRST(1-8)(dst2) 316 LOAD t1, FIRST(1)(src) 325 STORE t1, FIRST(-7)(dst2) 352 LOAD t1, FIRST(0)(dst) 356 and t1, mask, t1 # t1 [all...] |
/broadcom-cfe-1.4.2/cfe/arch/mips/cpu/bcmcore/include/ |
H A D | sbmips32.h | 141 #define t1 $9 macro
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/broadcom-cfe-1.4.2/cfe/arch/mips/chipset/sibyte/include/ |
H A D | sbmips.h | 191 #define t1 $9 macro
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