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/barrelfish-2018-10-04/kernel/arch/armv7/
H A Dpaging.c12 #include <cache.h>
168 /* Clean the modified entry to L2 cache. */
178 /* Clean the modified entry to L2 cache. */
269 printf("SECTION 0x%"PRIxLPADDR" buf=%d cache=%d xn=%d dom=0x%04x\n",
285 printf("SUPERSECTION 0x%"PRIxLPADDR" buf=%d cache=%d xn=%d dom=0x%04x\n",
402 /* Clean the modified entry to L2 cache. */
467 /* Clean the modified entry to L2 cache. */
534 /* Clean the modified entry to L2 cache. */
628 /* Clean the modified entry to L2 cache. */
700 /* Clean the modified entry to L2 cache
[all...]
/barrelfish-2018-10-04/lib/openssl-1.0.0d/crypto/x509/
H A Dx509_lu.c185 ret->cache=1;
499 /* Nothing found in cache: do lookup to possibly add new
500 * objects to cache
545 /* Check cache first */
548 /* Always do lookup to possibly add new CRLs to cache
615 * a given subject name. However it will fill the cache with all
616 * matching certificates, so we can examine the cache for all
/barrelfish-2018-10-04/usr/eclipseclp/Kernel/lib/
H A Ddebug.pl360 % We cannot cache more permanently because cwd and file system may change.
/barrelfish-2018-10-04/lib/lua/src/
H A Dlvm.c380 Closure *c = p->cache;
398 ** before the assignment to 'p->cache', as the function needs the
416 p->cache = ncl; /* save it on cache for reuse */
/barrelfish-2018-10-04/doc/017-arm/
H A DARM.tex192 the cache quirk workarounds for GEM5 and proper offsets for the
795 address at all times. They are also not cache-coherent with the
861 32-byte cache line size of the ARMv7 architecture. A notification
/barrelfish-2018-10-04/include/vm/
H A Dvm_object.c215 object->cache.rt_root = 0;
216 object->cache.rt_flags = 0;
1374 /* vm_page_rename() will handle dirty and cache. */
1477 * We do not want to have to test for the existence of cache or swap
1622 * cache.
/barrelfish-2018-10-04/doc/000-overview/
H A DOverview.tex64 cache-coherent shared RAM, and the rest of the OS does not use shared
67 address spaces (and therefore cache-coherent shared memory) between
410 is based on L4's RPC path, while between cache-coherent cores the
414 single cache lines without involving the kernel. Other ICDs exist
/barrelfish-2018-10-04/lib/devif/backends/net/mlx4/include/rdma/
H A Dib_verbs.h1174 struct ib_cache cache; member in struct:ib_device
/barrelfish-2018-10-04/doc/006-routing/
H A DRouting.tex80 \item \textbf{Cache}: If an ICD uses polling to check for incoming messages, the polled cache line will be placed in the cache. If the core has many ICD links, a significant part of its cache will be flushed due to polling.
/barrelfish-2018-10-04/doc/011-idc/
H A DIDC.tex1051 a cache line. The sender writes into the send buffer, and the receiver reads
1068 avoid bouncing cache lines the buffer is kept write-only for the sender and
/barrelfish-2018-10-04/doc/026-device-queues/
H A Ddevif.tex253 reside in the cache. Altering a buffer that a client has no ownership over,
315 dequeues a buffer, it has to invalidate its cache of the received buffer when
/barrelfish-2018-10-04/lib/devif/backends/net/mlx4/drivers/net/mlx4/
H A Dfw.c40 #include <linux/cache.h>
49 #include <linux/cache.h>
/barrelfish-2018-10-04/lib/tommath/
H A Dtommath.tex2815 one mp\_word per iteration. On processors such as the Athlon XP and P4 this did not matter much since the cache bandwidth
2816 is very high and it can keep the ALU fed with data. It did, however, matter on older and embedded cpus where cache is often
2910 \item To a lesser extent memory bandwidth and function call overheads. Provided the values are in the processor cache this is less of an

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