Searched refs:base (Results 226 - 250 of 464) sorted by relevance

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/barrelfish-2018-10-04/lib/lua/src/
H A Dldebug.c109 if (n >= ci->u.l.base - ci->func - nparams)
121 StkId base; local
126 base = ci->u.l.base;
131 base = ci->func + 1;
134 if (limit - base >= n && n > 0) /* is 'n' inside 'ci' stack? */
139 *pos = base + (n - 1);
356 if (reg >= a + 2) /* affect all regs above its base */
362 if (reg >= a) /* affect all registers above base */
493 for (p = ci->u.l.base;
[all...]
/barrelfish-2018-10-04/usr/eclipseclp/documents/megalog/
H A Dintro-sec.tex33 next generation Data\-base \& Knowledge Base Management Systems.
34 \eclipse integrates a knowledge base with a logic programming
41 This manual is restricted to the database and knowledge base aspects of
54 knowledge base.
76 The database and knowledge base systems are implemented as several \eclipse
92 base. It provides a direct access to the database without going through
111 This module contains the user's knowledge base itself. For further details
/barrelfish-2018-10-04/lib/devif/backends/net/mlx4/drivers/net/mlx4/
H A Dqp.c221 int *base, u8 flags) {
232 *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align,
234 if (*base == -1)
240 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base, argument
256 *base = get_param_l(&out_param);
259 return __mlx4_qp_reserve_range(priv, cnt, align, base, flags);
287 " base:%d cnt:%d\n", base_qpn, cnt);
220 __mlx4_qp_reserve_range(struct mlx4_priv *priv, int cnt, int align, int *base, u8 flags) argument
/barrelfish-2018-10-04/usr/drivers/megaraid/
H A Dmegaraid.c164 genvaddr_t base = vregion_get_base_addr(&mmu_state->vregion); local
173 /* (void *)(base + i->offset), */
174 /* (void *)(base + i->offset + i->size)); */
175 if(base + i->offset <= (genvaddr_t)ptr &&
176 ((genvaddr_t)ptr) + len < base + i->offset + i->size) {
179 /* buf->pa = id.base + ((genvaddr_t)ptr - base - i->offset); */
180 paddr = i->pa + ((genvaddr_t)ptr - base - i->offset);
226 id->base = cap.paddr;
240 *paddr = id.base;
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/barrelfish-2018-10-04/usr/acpi/
H A Dintel_vtd.c106 assert(regset_base == regset_frame_id.base);
122 rt_base = rt_frame_id.base;
179 assert((ct_id.base & BASE_PAGE_MASK) == 0);
180 vtd_root_entry_ctp_insert(unit->root_table[i], (ct_id.base >> BASE_PAGE_BITS));
186 // the base physical address of it. If not, we return 0.
193 genpaddr_t pt = pml4_id.base;
200 // from a frame capability, instead of the base address of the empty
202 pml4_id.base = 0;
206 if (pml4_id.base == pt) {
348 genpaddr_t pt = pml4_id.base;
[all...]
/barrelfish-2018-10-04/lib/libc/stdlib/jemalloc/
H A DMakefile.inc5 JEMALLOCSRCS:= jemalloc.c arena.c atomic.c base.c bitmap.c chunk.c \
/barrelfish-2018-10-04/kernel/arch/arm/
H A Domap_uart.c49 void omap_uart_init(unsigned port, lvaddr_t base, bool initialize_hw) argument
53 omap44xx_uart3_initialize(&ports[port], (mackerel_addr_t)base);
/barrelfish-2018-10-04/kernel/arch/armv7/
H A Dpaging.c319 lvaddr_t base = 0; local
321 for(i = 0; i < ARM_L1_MAX_ENTRIES; i++, base += ARM_L1_SECTION_BYTES ) {
322 paging_print_l1_pte(base, l1_high[i]);
325 base = 0;
326 for(i = 0; i < ARM_L1_MAX_ENTRIES; i++, base += ARM_L1_SECTION_BYTES ) {
327 paging_print_l1_pte(base, l1_low[i]);
620 lvaddr_t base = local_phys_to_mem(get_address(&info->ptable->cap)) + local
625 (union arm_l2_entry *)base + i;
H A Dplat_zynq7.c49 lvaddr_t base = paging_map_device(uart_base[port], uart_size[port]); local
50 zynq_uart_init(port, base, initialize_hw);
/barrelfish-2018-10-04/usr/bench/dma/
H A Ddma_bench.c67 frame_addr = id.base;
92 frame_addr2 = id2.base;
/barrelfish-2018-10-04/usr/drivers/cpuboot/arch/x86/
H A Dboot_arch.c470 elf64_relocate(frameid.base + arch_page_size, state.elfbase,
489 elf32_relocate(frameid.base + arch_page_size, state.elfbase,
523 DEBUG("%s:%s:%d: urpc_frame_id.base=%"PRIxGENPADDR"\n",
524 __FILE__, __FUNCTION__, __LINE__, urpc_frame_id.base);
648 + frameid.base + arch_page_size;
672 core_data->urpc_frame_base = urpc_frame_id.base;
677 core_data->memory_base_start = spawn_memory_identity.base;
691 DEBUG("%s:%s:%d: fid.base is 0x%"PRIxGENPADDR"\n",
692 __FILE__, __FUNCTION__, __LINE__, fid.base);
693 core_data->kcb = (genpaddr_t) fid.base;
[all...]
/barrelfish-2018-10-04/usr/drivers/ioat_dma/
H A Dmain.c76 .src = id.base,
77 .dst = id.base + BUFFER_SIZE,
/barrelfish-2018-10-04/usr/drivers/usb/usb_manager/
H A Dusb_memory.c106 ret->page.phys_addr = ret->frame_id.base;
180 ret->phys_addr = ret->frame_id.base;
/barrelfish-2018-10-04/lib/barrelfish/
H A Dbulk_transfer.c68 current_pbuf->base = (char *)mem + current_pbuf->offset;
83 current_pbuf->base = (char *)mem + current_pbuf->offset;
/barrelfish-2018-10-04/lib/barrelfish/vspace/
H A Dmemobj_one_frame_one_map.c73 genvaddr_t base = vregion_get_base_addr(vregion); local
77 err = pmap->f.modify_flags(pmap, base + offset + vregion_offset, range,
H A Dmmu_aware.c267 lvaddr_t base, size_t bytes)
274 genvaddr_t gen_base = vspace_lvaddr_to_genvaddr(base)
279 assert(vspace_lvaddr_to_genvaddr(base) >= vregion_get_base_addr(&state->vregion));
280 assert(base + bytes == (lvaddr_t)eaddr);
292 // Unmap and return (via unfill) frames from base
266 vspace_mmu_aware_unmap(struct vspace_mmu_aware *state, lvaddr_t base, size_t bytes) argument
/barrelfish-2018-10-04/usr/monitor/
H A Dboot.c35 b->ump_state.chan.recvid = (uintptr_t)umpid.base;
37 (umpid.base + channel_length);
/barrelfish-2018-10-04/usr/tests/mdbtests/
H A Dtest_ops_with_root.c71 out[gencount].cap.u.ram = (struct RAM) { .base = begin, .bits = sizebits };
92 ranges[i].cap.u.ram.base, ranges[i].cap.u.ram.bits);
/barrelfish-2018-10-04/lib/libc/gen/
H A Dnftw.c96 ftw.base = cur->fts_pathlen - cur->fts_namelen;
/barrelfish-2018-10-04/usr/drivers/usb/usb_manager/controller/ehci/
H A Dusb_ehci.c321 * \param base the base address of the ehci controller
323 usb_error_t usb_ehci_init(usb_ehci_hc_t *hc, uintptr_t base) argument
331 ehci_initialize(&hc->ehci_base, (mackerel_addr_t) base, NULL);
341 ehci_initialize(&hc->ehci_base, (mackerel_addr_t) base,
342 (mackerel_addr_t) (base + cap_offset));
/barrelfish-2018-10-04/usr/drivers/vbe/
H A Dint10.c297 unsigned char* base = xf86MapVidMem(pInt->scrnIndex,
303 mem_ww(pInt, i, *(base + i));
306 *(base + i) = MEM_RW(pInt, i);
309 xf86UnMapVidMem(pInt->scrnIndex,base,pagesize);
/barrelfish-2018-10-04/usr/drivers/xeon_phi/
H A Dinterphi.c82 uint64_t base; member in struct:interphi_msg_st::__anon1598::__anon1602
382 st->args.bootstrap.base,
744 uint64_t base,
751 base, bits, offset, xid, is_client);
774 msg_st->err = sysmem_cap_request(base, bits, &msg_frame);
1035 id.base, (uintptr_t )addr, frame_size);
1051 mi->fi.sendbase = id.base;
1060 mi->fi.sendbase = id.base + mi->fi.outbufsize;
1088 err = interphi_bootstrap(phi, id.base, log2ceil(id.bytes), offset, xphi, mi->is_client);
1157 id.base, (uintptr_
743 bootstrap_call_rx(struct interphi_binding *_binding, uint64_t base, uint64_t offset, uint8_t bits, uint8_t xid, uint8_t is_client) argument
[all...]
/barrelfish-2018-10-04/include/barrelfish/
H A Ddebug.h46 void debug_dump_mem(lvaddr_t base, lvaddr_t limit, lvaddr_t point);
/barrelfish-2018-10-04/include/lwip2/lwip/priv/
H A Dmemp_priv.h148 u8_t *base; member in struct:memp_desc
/barrelfish-2018-10-04/lib/blk/blk_ahci/
H A Dblk_ahci.h33 /// Data base address
113 errval_t blk_ahci_port_dma_async(struct ahci_port *port, size_t slot, uint64_t block, lpaddr_t base, size_t length, bool write);

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