Searched refs:base (Results 101 - 125 of 464) sorted by relevance

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/barrelfish-2018-10-04/lib/lwip2/src/core/ipv4/
H A Dip4_addr.c158 u8_t base; local
174 base = 10;
178 base = 16;
181 base = 8;
186 val = (val * base) + (u32_t)(c - '0');
188 } else if (base == 16 && isxdigit(c)) {
/barrelfish-2018-10-04/kernel/include/arch/armv8/
H A Dpaging_kernel_arch.h40 uint64_t base :36; // base address of next level table member in struct:armv8_ttable_entry::__anon419
58 uint64_t base :18; member in struct:armv8_ttable_entry::__anon420
77 uint64_t base :27; member in struct:armv8_ttable_entry::__anon421
95 uint64_t base :36; member in struct:armv8_ttable_entry::__anon422
120 lvaddr_t paging_map_device(lpaddr_t base, size_t size);
145 void paging_make_good(lpaddr_t base);
/barrelfish-2018-10-04/lib/arranet/
H A Dip_addr.c156 u8_t base; local
171 base = 10;
175 base = 16;
178 base = 8;
182 val = (val * base) + (int)(c - '0');
184 } else if (base == 16 && isxdigit(c)) {
/barrelfish-2018-10-04/lib/lwip2/src/core/
H A Ddef.c200 const int base = 10; local
207 number /= base;
208 *ptr++ = "zyxwvutsrqponmlkjihgfedcba9876543210123456789abcdefghijklmnopqrstuvwxyz"[35 + (tmp_value - number * base)];
/barrelfish-2018-10-04/kernel/arch/x86_32/
H A Dexec.c141 "movl 0*4(%[regs]), %%eax \n\t" // EAX was base register
183 * \param base Virtual address of 64-bit word to monitor
188 * Returns when the 64-bit word at base is not equal to lastval.
190 void monitor_mwait(lvaddr_t base, uint64_t lastval, uint32_t extensions, argument
193 volatile uint64_t *val = (uint64_t *)base;
199 monitor(base, extensions, hints);
H A Dinit.c241 lvaddr_t vbase = X86_32_MEMORY_OFFSET, base = 0; local
250 base += X86_32_MEM_PAGE_SIZE, vbase += X86_32_MEM_PAGE_SIZE) {
252 paging_x86_32_map_pdpte(&boot_pdpte[X86_32_PDPTE_BASE(base)],
254 paging_x86_32_map_large(&boot_pdir[X86_32_PDIR_BASE(base)], base,
262 paging_x86_32_map_large(&boot_pdir_hi[X86_32_PDIR_BASE(vbase)], base,
272 base += X86_32_MEM_PAGE_SIZE, vbase += X86_32_MEM_PAGE_SIZE) {
275 paging_x86_32_map_large(&boot_pdir[X86_32_PDIR_BASE(base)], base,
281 paging_x86_32_map_large(&boot_pdir[X86_32_PDIR_BASE(vbase)], base,
[all...]
/barrelfish-2018-10-04/usr/drivers/serial/
H A Dserial_pl011.c52 lvaddr_t base; local
54 err= map_device_register(membase, BASE_PAGE_SIZE, &base);
60 pl011_uart_initialize(&uart, (mackerel_addr_t) base);
/barrelfish-2018-10-04/include/arch/k1om/barrelfish_kpi/
H A Dasm_inlines_arch.h184 static inline void cache_flush_range(void *base, size_t len)
188 uint8_t *line = (uint8_t *)((uintptr_t)base & ~(CACHE_LINE_SIZE-1UL));
192 }while (line < (uint8_t *)base + len);
/barrelfish-2018-10-04/usr/tests/memtest/
H A Dmem_free.c40 cap.u.ram.base, cap.u.ram.bits);
58 cap.u.ram.base, cap.u.ram.bits);
64 cap.u.ram.base, cap.u.ram.bits);
/barrelfish-2018-10-04/kernel/arch/arm/
H A Dpl011.c78 void pl011_init(unsigned port, lvaddr_t base, bool hwinit) argument
86 pl011_uart_initialize(u, (mackerel_addr_t) base);
142 assert(u->base != 0);
155 assert(u->base != 0);
H A Dzynq_uart.c48 zynq_uart_init(unsigned port, lvaddr_t base, bool initialize_hw) { argument
50 zynq_uart_initialize(&ports[port], (mackerel_addr_t) base);
/barrelfish-2018-10-04/kernel/arch/armv8/
H A Dplat_apm88xxxx.c41 if ((lpaddr_t)ports[port].base == (uart_base[port] + KERNEL_OFFSET)) {
65 if ((lpaddr_t)ports[port].base == uart_base[port]) {
86 assert(ports[port].base != 0);
100 assert(ports[port].base != 0);
H A Dpaging.c109 l2.block_l2.base = pa >> 21u;
121 l1.block_l1.base = pa >> 30u;
158 e.d.base = (pa >> BASE_PAGE_BITS);
173 e.d.base = (pa >> BASE_PAGE_BITS);
189 e.block_l1.base = (pa >> BASE_PAGE_BITS);
206 e.d.base = (pa >> BASE_PAGE_BITS);
224 e.block_l2.base = (pa >> BASE_PAGE_BITS);
245 e.page.base = (pa >> BASE_PAGE_BITS);
263 e.page.base = (pa >> BASE_PAGE_BITS);
265 // printf("Setting l3 entry@%p -> (%p) %p raw: %p\n", l3_entry, e.page.base,
738 lvaddr_t base = local_phys_to_mem(get_address(&info->ptable->cap)) + local
[all...]
H A Dplat_cn88xx.c73 lvaddr_t base = local_phys_to_mem(uart_base[port]); local
74 pl011_init(port, base, initialize_hw);
H A Dplat_qemu.c77 lvaddr_t base = local_phys_to_mem(uart_base[port]); local
78 pl011_init(port, base, initialize_hw);
/barrelfish-2018-10-04/kernel/arch/k1om/
H A Dinit.c167 .base = 0
185 .base = 0 // changed by context switch path when doing lldt
237 * \param base Start address of kernel image in physical address space.
240 static void paging_init(lpaddr_t base, size_t size) argument
242 lvaddr_t vbase = local_phys_to_mem(base);
244 // Align base to kernel page size
245 if(base & X86_64_MEM_PAGE_MASK) {
246 size += base & X86_64_MEM_PAGE_MASK;
247 base -= base
[all...]
/barrelfish-2018-10-04/kernel/arch/x86_64/
H A Dinit.c159 .base = 0
177 .base = 0 // changed by context switch path when doing lldt
222 * \param base Start address of kernel image in physical address space.
225 static void paging_init(lpaddr_t base, size_t size) argument
227 lvaddr_t vbase = local_phys_to_mem(base);
229 // Align base to kernel page size
230 if(base & X86_64_MEM_PAGE_MASK) {
231 size += base & X86_64_MEM_PAGE_MASK;
232 base -= base
[all...]
H A Dvmkit.c42 lpaddr_t lpaddr = gen_phys_to_local_phys(dcb->guest_desc.ctrl.cap.u.frame.base);
47 lpaddr = gen_phys_to_local_phys(dcb->guest_desc.vmcb.cap.u.frame.base);
/barrelfish-2018-10-04/usr/acpi/arch/x86/
H A Dioapic.h29 errval_t ioapic_init(struct ioapic *a, lvaddr_t base, uint8_t id,
/barrelfish-2018-10-04/include/barrelfish/
H A Dheap.h35 union heap_header base; /* allocated list head */ member in struct:heap
/barrelfish-2018-10-04/usr/kaluga/
H A Ddevice_caps.c49 if (address >= iter->id.base &&
50 (address + size <= (iter->id.base + iter->id.bytes))) {
106 err = mm_init(&register_manager, ObjType_DevFrame, ret.base, capbits, 1,
113 err= mm_add(&register_manager, requested_cap, capbits, ret.base);
/barrelfish-2018-10-04/usr/pci/
H A Dpci.c71 if (bar.base == 0) {
77 if (bar.base & mask) {
83 static pciaddr_t bar_mapping_size64(uint64_t base) argument
85 if (base == 0) {
91 if (base & mask) {
94 * the bar.base value so no shift.
150 pciaddr_t base,
168 err = acl->rpc_tx_vtbl.mm_alloc_range_proxy(acl, bits, base,
169 base + framesize,
174 PCI_DEBUG("mm_alloc_range() failed: bits = %hhu, base
145 alloc_device_bar(uint8_t idx, uint8_t bus, uint8_t dev, uint8_t fun, uint8_t BAR, pciaddr_t base, pciaddr_t high, pcisize_t size) argument
1271 program_bridge_window(uint8_t bus, uint8_t dev, uint8_t fun, pciaddr_t base, pciaddr_t high, bool pcie, bool mem, bool pref) argument
1347 program_device_bar(uint8_t bus, uint8_t dev, uint8_t fun, int bar, pciaddr_t base, pcisize_t size, int bits, bool memspace, bool pcie) argument
1438 pciaddr_t base, high; local
[all...]
/barrelfish-2018-10-04/kernel/arch/armv7/
H A Dplat_vexpress.c42 lvaddr_t base = paging_map_device(uart_base[port], uart_size[port]); local
43 pl011_init(port, base, initialize_hw);
/barrelfish-2018-10-04/kernel/include/arch/x86_32/
H A Dpaging_kernel_arch.h67 * Assigns given physical base address to the CR3 register,
71 * \param addr Physical base address of page table.
78 static lvaddr_t inline paging_map_device(lpaddr_t base, size_t size) argument
80 return paging_x86_32_map_device(base, size);
/barrelfish-2018-10-04/kernel/include/arch/x86_64/
H A Dx86.h107 static inline void monitor(lvaddr_t base, uint32_t extensions, uint32_t hints) argument
112 "a" (base),

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