| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-integrator/ |
| H A D | integrator_ap.c | 195 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
249 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
252 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
266 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
269 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
314 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
360 return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
409 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
424 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/video/geode/ |
| H A D | display_gx1.c | 66 bank_cfg = readl(mc_regs + MC_BANK_CFG);
74 fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
89 readl(par->dc_regs + DC_UNLOCK);
92 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
93 tcfg = readl(par->dc_regs + DC_TIMING_CFG);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/vlynq/ |
| H A D | vlynq.c | 113 if (readl(&dev->local->status) & VLYNQ_STATUS_LINK)
123 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET,
130 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET,
145 val = readl(&dev->remote->int_device[virq >> 2]);
158 val = readl(&dev->remote->int_device[virq >> 2]);
171 val = readl(&dev->remote->int_device[virq >> 2]);
198 u32 status = readl(&dev->local->status);
209 u32 status = readl(&dev->remote->status);
222 status = readl(&dev->local->int_status);
272 writel(readl(
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/tile/include/asm/ |
| H A D | io.h | 137 #define readl(addr) _tile_readl((unsigned long)addr) macro
146 #define __raw_readl readl
155 #define readl_relaxed readl
160 #define ioread32 readl
173 *(u32 *)(dst + x) = readl(src + x);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mn10300/include/asm/ |
| H A D | io.h | 37 static inline u32 readl(const volatile void __iomem *addr) function
44 #define __raw_readl readl
48 #define readl_relaxed readl
95 return readl((volatile void __iomem *) addr);
189 #define ioread32(addr) readl(addr)
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/tile/include/asm/ |
| H A D | io.h | 137 #define readl(addr) _tile_readl((unsigned long)addr) macro
146 #define __raw_readl readl
155 #define readl_relaxed readl
160 #define ioread32 readl
173 *(u32 *)(dst + x) = readl(src + x);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/video/geode/ |
| H A D | display_gx1.c | 66 bank_cfg = readl(mc_regs + MC_BANK_CFG);
74 fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
89 readl(par->dc_regs + DC_UNLOCK);
92 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
93 tcfg = readl(par->dc_regs + DC_TIMING_CFG);
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/vlynq/ |
| H A D | vlynq.c | 113 if (readl(&dev->local->status) & VLYNQ_STATUS_LINK)
123 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET,
130 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET,
145 val = readl(&dev->remote->int_device[virq >> 2]);
158 val = readl(&dev->remote->int_device[virq >> 2]);
171 val = readl(&dev->remote->int_device[virq >> 2]);
198 u32 status = readl(&dev->local->status);
209 u32 status = readl(&dev->remote->status);
222 status = readl(&dev->local->int_status);
272 writel(readl(
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/common/ |
| H A D | gic.c | 131 val = readl(base + GIC_DIST_CONFIG + confoff);
141 if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
166 val = readl(reg) & ~(0xff << shift);
186 status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
244 max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mn10300/include/asm/ |
| H A D | io.h | 37 static inline u32 readl(const volatile void __iomem *addr) function
44 #define __raw_readl readl
48 #define readl_relaxed readl
95 return readl((volatile void __iomem *) addr);
189 #define ioread32(addr) readl(addr)
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/common/ |
| H A D | gic.c | 131 val = readl(base + GIC_DIST_CONFIG + confoff);
141 if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
166 val = readl(reg) & ~(0xff << shift);
186 status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
244 max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/net/ |
| H A D | sungem.c | 153 cmd = readl(gp->regs + MIF_FRAME);
191 cmd = readl(gp->regs + MIF_FRAME);
257 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
277 (readl(gp->regs + PCS_MIISTAT) &
312 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
375 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
388 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
401 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
417 if (!(readl(g
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/net/ |
| H A D | sungem.c | 153 cmd = readl(gp->regs + MIF_FRAME);
191 cmd = readl(gp->regs + MIF_FRAME);
257 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
277 (readl(gp->regs + PCS_MIISTAT) &
312 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
375 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
388 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
401 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
417 if (!(readl(g
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/mmc/host/ |
| H A D | via-sdmmc.c | 338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbas
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/mmc/host/ |
| H A D | via-sdmmc.c | 338 readl(addrbase + VIA_CRDR_SDCTRL),
339 readl(addrbase + VIA_CRDR_SDCARG),
340 readl(addrbase + VIA_CRDR_SDBUSMODE));
342 readl(addrbase + VIA_CRDR_SDBLKLEN),
343 readl(addrbase + VIA_CRDR_SDCURBLKCNT),
344 readl(addrbase + VIA_CRDR_SDINTMASK));
346 readl(addrbase + VIA_CRDR_SDSTATUS),
347 readl(addrbase + VIA_CRDR_SDCLKSEL),
348 readl(addrbase + VIA_CRDR_SDEXTCTRL));
409 pm_sdhc_reg->sdcontrol_reg = readl(addrbas
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/mtd/nand/ |
| H A D | sh_flctl.c | 138 val = readl(FLDTCNTR(flctl)) >> 16;
152 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
171 size = readl(FLDTCNTR(flctl)) >> 24;
175 if (readl(FL4ECCCR(flctl)) & _4ECCFA)
179 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND))
189 data = readl(ecc_reg[i]);
220 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
235 data = readl(FLDATAR(flctl));
249 buf[i] = readl(fifo_addr);
263 ecc_buf[i] = readl(fifo_add
[all...] |
| H A D | cmx270_nand.c | 59 return (readl(this->IO_ADDR_R) >> 16);
77 *buf++ = readl(this->IO_ADDR_R) >> 16;
86 if (buf[i] != (u_char)(readl(this->IO_ADDR_R) >> 16))
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/spi/ |
| H A D | spi_s3c64xx.c | 192 val = readl(regs + S3C64XX_SPI_CH_CFG);
200 val = readl(regs + S3C64XX_SPI_STATUS);
209 val = readl(regs + S3C64XX_SPI_STATUS);
211 readl(regs + S3C64XX_SPI_RX_DATA);
219 val = readl(regs + S3C64XX_SPI_CH_CFG);
223 val = readl(regs + S3C64XX_SPI_MODE_CFG);
227 val = readl(regs + S3C64XX_SPI_CH_CFG);
240 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
243 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
338 status = readl(reg
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/comedi/drivers/ |
| H A D | gsc_hpdi.c | 418 readl(plx_iobase + PLX_INTRCS_REG));
419 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
421 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
424 readl(plx_iobase + PLX_REVISION_REG));
426 readl(plx_iobase + PLX_DMA0_MODE_REG));
428 readl(plx_iobase + PLX_DMA1_MODE_REG));
430 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
432 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
434 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
436 readl(plx_iobas
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/spi/ |
| H A D | spi_s3c64xx.c | 192 val = readl(regs + S3C64XX_SPI_CH_CFG);
200 val = readl(regs + S3C64XX_SPI_STATUS);
209 val = readl(regs + S3C64XX_SPI_STATUS);
211 readl(regs + S3C64XX_SPI_RX_DATA);
219 val = readl(regs + S3C64XX_SPI_CH_CFG);
223 val = readl(regs + S3C64XX_SPI_MODE_CFG);
227 val = readl(regs + S3C64XX_SPI_CH_CFG);
240 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
243 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
338 status = readl(reg
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/mtd/nand/ |
| H A D | sh_flctl.c | 138 val = readl(FLDTCNTR(flctl)) >> 16;
152 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
171 size = readl(FLDTCNTR(flctl)) >> 24;
175 if (readl(FL4ECCCR(flctl)) & _4ECCFA)
179 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND))
189 data = readl(ecc_reg[i]);
220 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
235 data = readl(FLDATAR(flctl));
249 buf[i] = readl(fifo_addr);
263 ecc_buf[i] = readl(fifo_add
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/comedi/drivers/ |
| H A D | gsc_hpdi.c | 418 readl(plx_iobase + PLX_INTRCS_REG));
419 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
421 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
424 readl(plx_iobase + PLX_REVISION_REG));
426 readl(plx_iobase + PLX_DMA0_MODE_REG));
428 readl(plx_iobase + PLX_DMA1_MODE_REG));
430 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
432 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
434 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
436 readl(plx_iobas
[all...] |
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/drm/ |
| H A D | drm_os_linux.h | 12 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
31 #define DRM_READ32(map, offset) readl(((void __iomem *)(map)->handle) + (offset))
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/infiniband/hw/mthca/ |
| H A D | mthca_catas.c | 100 switch (swab32(readl(dev->catas_err.map)) >> 24) {
121 i, swab32(readl(dev->catas_err.map + i)));
138 if (readl(dev->catas_err.map + i)) {
|
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/infiniband/hw/mthca/ |
| H A D | mthca_catas.c | 100 switch (swab32(readl(dev->catas_err.map)) >> 24) {
121 i, swab32(readl(dev->catas_err.map + i)));
138 if (readl(dev->catas_err.map + i)) {
|