Searched refs:PLL_CTL (Results 26 - 38 of 38) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf561/include/mach/
H A DdefBF561.h23 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
H A DcdefBF561.h23 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1537 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1553 bfin_write16(PLL_CTL, val);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF534.h19 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1753 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1767 bfin_write16(PLL_CTL, val);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
2030 /* Writing to PLL_CTL initiates a PLL relock sequence. */
2046 bfin_write16(PLL_CTL, val);
H A DdefBF539.h20 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf561/include/mach/
H A DcdefBF561.h23 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1537 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1553 bfin_write16(PLL_CTL, val);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DcdefBF534.h19 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
1753 /* Writing to PLL_CTL initiates a PLL relock sequence. */
1767 bfin_write16(PLL_CTL, val);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
2030 /* Writing to PLL_CTL initiates a PLL relock sequence. */
2046 bfin_write16(PLL_CTL, val);
H A DdefBF539.h20 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h17 #define PLL_CTL 0xffc00000 /* PLL Control Register */ macro
H A DcdefBF54x_base.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
2651 /* Writing to PLL_CTL initiates a PLL relock sequence. */
2669 bfin_write16(PLL_CTL, val);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h17 #define PLL_CTL 0xffc00000 /* PLL Control Register */ macro
H A DcdefBF54x_base.h20 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
2651 /* Writing to PLL_CTL initiates a PLL relock sequence. */
2669 bfin_write16(PLL_CTL, val);

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