Searched refs:MC2 (Results 26 - 38 of 38) sorted by relevance
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/media/ |
| H A D | saa7146.h | 367 #define MC2 0x100 /* Main control register 2 */ macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/media/video/ |
| H A D | hexium_gemini.c | 382 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
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| H A D | mxb.c | 376 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/media/video/ |
| H A D | hexium_gemini.c | 382 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
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| H A D | mxb.c | 376 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/include/asm/ |
| H A D | bfin_can.h | 185 #define MC2 0x0004 /* Enable Mailbox 2 */ macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/include/asm/ |
| H A D | bfin_can.h | 185 #define MC2 0x0004 /* Enable Mailbox 2 */ macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/media/dvb/ttpci/ |
| H A D | av7110_v4l.c | 773 saa7146_write(av7110->dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
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| H A D | budget-av.c | 1470 saa7146_write(dev, MC2, MASK_09 | MASK_25 | MASK_10 | MASK_26);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/media/dvb/ttpci/ |
| H A D | av7110_v4l.c | 773 saa7146_write(av7110->dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
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| H A D | budget-av.c | 1470 saa7146_write(dev, MC2, MASK_09 | MASK_25 | MASK_10 | MASK_26);
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/sound/pci/ |
| H A D | intel8x0.c | 128 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/sound/pci/ |
| H A D | intel8x0.c | 128 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
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