Searched refs:IDESC (Results 76 - 100 of 186) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/cris/
H A Dcris-tmpl.c272 const IDESC *idesc,
286 const IDESC *idesc,
304 const IDESC *idesc,
320 const IDESC *idesc,
335 const IDESC *idesc,
355 const IDESC *idesc,
379 const IDESC *idesc ATTRIBUTE_UNUSED,
H A Dcrisv10f.c34 const IDESC *idesc ATTRIBUTE_UNUSED,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/m32r/
H A Ddecode2.h27 extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR,
138 extern int m32r2f_model_m32r2_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
139 extern int m32r2f_model_m32r2_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
140 extern int m32r2f_model_m32r2_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
141 extern int m32r2f_model_m32r2_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
142 extern int m32r2f_model_m32r2_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
143 extern int m32r2f_model_m32r2_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
H A Ddecodex.h27 extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR,
136 extern int m32rxf_model_m32rx_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
137 extern int m32rxf_model_m32rx_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
138 extern int m32rxf_model_m32rx_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
139 extern int m32rxf_model_m32rx_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
140 extern int m32rxf_model_m32rx_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
141 extern int m32rxf_model_m32rx_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
H A Ddecode.c35 static IDESC m32rbf_insn_data[M32RBF_INSN__MAX];
158 /* Initialize an IDESC from the compile-time computable parts. */
161 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
191 IDESC *id,*tabend;
194 IDESC *table = m32rbf_insn_data;
196 memset (table, 0, tabsize * sizeof (IDESC));
210 /* Link the IDESC table into the cpu. */
214 /* Given an instruction, return a pointer to its IDESC entry. */
216 const IDESC *
475 const IDESC *ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/sh64/
H A Ddecode-compact.c35 static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN__MAX];
248 /* Initialize an IDESC from the compile-time computable parts. */
251 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
281 IDESC *id,*tabend;
284 IDESC *table = sh64_compact_insn_data;
286 memset (table, 0, tabsize * sizeof (IDESC));
300 /* Link the IDESC table into the cpu. */
304 /* Given an instruction, return a pointer to its IDESC entry. */
306 const IDESC *
3012 const IDESC *ides
[all...]
H A Dmloop-compact.c19 sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
50 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
65 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
74 static INLINE const IDESC *
78 const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
111 const IDESC *idesc = abuf->idesc;
236 const IDESC *idesc;
289 const IDESC *id;
437 const IDESC *cur_idesc = cur_abuf->idesc;
451 const IDESC *prev_ides
[all...]
H A Dmloop-media.c19 sh64_media_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
50 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEFORE];
65 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_AFTER];
74 static INLINE const IDESC *
78 const IDESC *id = sh64_media_decode (current_cpu, pc, insn, insn, abuf);
111 const IDESC *idesc = abuf->idesc;
236 const IDESC *idesc;
276 const IDESC *id;
424 const IDESC *cur_idesc = cur_abuf->idesc;
438 const IDESC *prev_ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/sh64/
H A Ddecode-compact.c35 static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN__MAX];
248 /* Initialize an IDESC from the compile-time computable parts. */
251 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
281 IDESC *id,*tabend;
284 IDESC *table = sh64_compact_insn_data;
286 memset (table, 0, tabsize * sizeof (IDESC));
300 /* Link the IDESC table into the cpu. */
304 /* Given an instruction, return a pointer to its IDESC entry. */
306 const IDESC *
3012 const IDESC *ides
[all...]
H A Dmloop-compact.c19 sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
50 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
65 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
74 static INLINE const IDESC *
78 const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
111 const IDESC *idesc = abuf->idesc;
236 const IDESC *idesc;
289 const IDESC *id;
437 const IDESC *cur_idesc = cur_abuf->idesc;
451 const IDESC *prev_ides
[all...]
H A Dmloop-media.c19 sh64_media_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
50 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEFORE];
65 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_AFTER];
74 static INLINE const IDESC *
78 const IDESC *id = sh64_media_decode (current_cpu, pc, insn, insn, abuf);
111 const IDESC *idesc = abuf->idesc;
236 const IDESC *idesc;
276 const IDESC *id;
424 const IDESC *cur_idesc = cur_abuf->idesc;
438 const IDESC *prev_ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/sh64/
H A Ddecode-compact.c35 static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN__MAX];
248 /* Initialize an IDESC from the compile-time computable parts. */
251 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
281 IDESC *id,*tabend;
284 IDESC *table = sh64_compact_insn_data;
286 memset (table, 0, tabsize * sizeof (IDESC));
300 /* Link the IDESC table into the cpu. */
304 /* Given an instruction, return a pointer to its IDESC entry. */
306 const IDESC *
3012 const IDESC *ides
[all...]
H A Dmloop-compact.c19 sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
50 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
65 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
74 static INLINE const IDESC *
78 const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
111 const IDESC *idesc = abuf->idesc;
236 const IDESC *idesc;
289 const IDESC *id;
437 const IDESC *cur_idesc = cur_abuf->idesc;
451 const IDESC *prev_ides
[all...]
H A Dmloop-media.c19 sh64_media_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
50 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEFORE];
65 const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_AFTER];
74 static INLINE const IDESC *
78 const IDESC *id = sh64_media_decode (current_cpu, pc, insn, insn, abuf);
111 const IDESC *idesc = abuf->idesc;
236 const IDESC *idesc;
276 const IDESC *id;
424 const IDESC *cur_idesc = cur_abuf->idesc;
438 const IDESC *prev_ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/m32r/
H A Ddecode.c35 static IDESC m32rbf_insn_data[M32RBF_INSN__MAX];
158 /* Initialize an IDESC from the compile-time computable parts. */
161 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
191 IDESC *id,*tabend;
194 IDESC *table = m32rbf_insn_data;
196 memset (table, 0, tabsize * sizeof (IDESC));
210 /* Link the IDESC table into the cpu. */
214 /* Given an instruction, return a pointer to its IDESC entry. */
216 const IDESC *
475 const IDESC *ides
[all...]
H A Dm32r2.c247 m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,
257 m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
267 m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,
277 m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,
296 m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,
305 m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
H A Dm32rx.c247 m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
257 m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
267 m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
277 m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
296 m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
305 m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/m32r/
H A Ddecode.c35 static IDESC m32rbf_insn_data[M32RBF_INSN__MAX];
158 /* Initialize an IDESC from the compile-time computable parts. */
161 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
191 IDESC *id,*tabend;
194 IDESC *table = m32rbf_insn_data;
196 memset (table, 0, tabsize * sizeof (IDESC));
210 /* Link the IDESC table into the cpu. */
214 /* Given an instruction, return a pointer to its IDESC entry. */
216 const IDESC *
475 const IDESC *ides
[all...]
H A Dm32r2.c247 m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc,
257 m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
267 m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc,
277 m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc,
296 m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc,
305 m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
H A Dm32rx.c247 m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
257 m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
267 m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
277 m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
296 m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
305 m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/frv/
H A Dprofile-fr400.c254 frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc,
261 frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc,
272 frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc,
282 frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
343 frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc,
404 frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc,
415 frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc,
425 frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
435 frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
446 frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/frv/
H A Dprofile-fr400.c254 frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc,
261 frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc,
272 frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc,
282 frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
343 frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc,
404 frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc,
415 frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc,
425 frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
435 frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
446 frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/frv/
H A Dprofile-fr400.c254 frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc,
261 frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc,
272 frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc,
282 frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
343 frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc,
404 frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc,
415 frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc,
425 frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
435 frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
446 frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *ides
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/cris/
H A Dcrisv10f.c34 const IDESC *idesc ATTRIBUTE_UNUSED,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/cris/
H A Dcrisv10f.c34 const IDESC *idesc ATTRIBUTE_UNUSED,

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