/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/m32r/ |
H A D | m32r2.c | 247 m32r2f_model_m32r2_u_exec (SIM_CPU *cpu, const IDESC *idesc, 257 m32r2f_model_m32r2_u_cmp (SIM_CPU *cpu, const IDESC *idesc, 267 m32r2f_model_m32r2_u_mac (SIM_CPU *cpu, const IDESC *idesc, 277 m32r2f_model_m32r2_u_cti (SIM_CPU *cpu, const IDESC *idesc, 296 m32r2f_model_m32r2_u_load (SIM_CPU *cpu, const IDESC *idesc, 305 m32r2f_model_m32r2_u_store (SIM_CPU *cpu, const IDESC *idesc,
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H A D | m32rx.c | 247 m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc, 257 m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc, 267 m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc, 277 m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc, 296 m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc, 305 m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,
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H A D | m32r.c | 340 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc, 350 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc, 360 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc, 370 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc, 389 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc, 399 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc, 409 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/cris/ |
H A D | decodev10.c | 36 static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX]; 258 /* Initialize an IDESC from the compile-time computable parts. */ 261 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 291 IDESC *id,*tabend; 294 IDESC *table = crisv10f_insn_data; 296 memset (table, 0, tabsize * sizeof (IDESC)); 310 /* Link the IDESC table into the cpu. */ 314 /* Given an instruction, return a pointer to its IDESC entry. */ 316 const IDESC * 3144 const IDESC *ides [all...] |
H A D | decodev32.c | 36 static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX]; 262 /* Initialize an IDESC from the compile-time computable parts. */ 265 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 295 IDESC *id,*tabend; 298 IDESC *table = crisv32f_insn_data; 300 memset (table, 0, tabsize * sizeof (IDESC)); 314 /* Link the IDESC table into the cpu. */ 318 /* Given an instruction, return a pointer to its IDESC entry. */ 320 const IDESC * 2616 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/cris/ |
H A D | decodev10.c | 36 static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX]; 258 /* Initialize an IDESC from the compile-time computable parts. */ 261 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 291 IDESC *id,*tabend; 294 IDESC *table = crisv10f_insn_data; 296 memset (table, 0, tabsize * sizeof (IDESC)); 310 /* Link the IDESC table into the cpu. */ 314 /* Given an instruction, return a pointer to its IDESC entry. */ 316 const IDESC * 3144 const IDESC *ides [all...] |
H A D | decodev32.c | 36 static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX]; 262 /* Initialize an IDESC from the compile-time computable parts. */ 265 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 295 IDESC *id,*tabend; 298 IDESC *table = crisv32f_insn_data; 300 memset (table, 0, tabsize * sizeof (IDESC)); 314 /* Link the IDESC table into the cpu. */ 318 /* Given an instruction, return a pointer to its IDESC entry. */ 320 const IDESC * 2616 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/cris/ |
H A D | decodev10.c | 36 static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX]; 258 /* Initialize an IDESC from the compile-time computable parts. */ 261 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 291 IDESC *id,*tabend; 294 IDESC *table = crisv10f_insn_data; 296 memset (table, 0, tabsize * sizeof (IDESC)); 310 /* Link the IDESC table into the cpu. */ 314 /* Given an instruction, return a pointer to its IDESC entry. */ 316 const IDESC * 3144 const IDESC *ides [all...] |
H A D | decodev32.c | 36 static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX]; 262 /* Initialize an IDESC from the compile-time computable parts. */ 265 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 295 IDESC *id,*tabend; 298 IDESC *table = crisv32f_insn_data; 300 memset (table, 0, tabsize * sizeof (IDESC)); 314 /* Link the IDESC table into the cpu. */ 318 /* Given an instruction, return a pointer to its IDESC entry. */ 320 const IDESC * 2616 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/sh64/ |
H A D | decode-media.c | 35 static IDESC sh64_media_insn_data[SH64_MEDIA_INSN__MAX]; 262 /* Initialize an IDESC from the compile-time computable parts. */ 265 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 295 IDESC *id,*tabend; 298 IDESC *table = sh64_media_insn_data; 300 memset (table, 0, tabsize * sizeof (IDESC)); 314 /* Link the IDESC table into the cpu. */ 318 /* Given an instruction, return a pointer to its IDESC entry. */ 320 const IDESC * 1536 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/sh64/ |
H A D | decode-media.c | 35 static IDESC sh64_media_insn_data[SH64_MEDIA_INSN__MAX]; 262 /* Initialize an IDESC from the compile-time computable parts. */ 265 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 295 IDESC *id,*tabend; 298 IDESC *table = sh64_media_insn_data; 300 memset (table, 0, tabsize * sizeof (IDESC)); 314 /* Link the IDESC table into the cpu. */ 318 /* Given an instruction, return a pointer to its IDESC entry. */ 320 const IDESC * 1536 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/sh64/ |
H A D | decode-media.c | 35 static IDESC sh64_media_insn_data[SH64_MEDIA_INSN__MAX]; 262 /* Initialize an IDESC from the compile-time computable parts. */ 265 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 295 IDESC *id,*tabend; 298 IDESC *table = sh64_media_insn_data; 300 memset (table, 0, tabsize * sizeof (IDESC)); 314 /* Link the IDESC table into the cpu. */ 318 /* Given an instruction, return a pointer to its IDESC entry. */ 320 const IDESC * 1536 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/m32r/ |
H A D | m32r.c | 340 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc, 350 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc, 360 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc, 370 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc, 389 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc, 399 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc, 409 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/m32r/ |
H A D | m32r.c | 340 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc, 350 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc, 360 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc, 370 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc, 389 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc, 399 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc, 409 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/frv/ |
H A D | profile-fr550.c | 419 frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc, 426 frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc, 461 frvbf_model_fr550_u_imul (SIM_CPU *cpu, const IDESC *idesc, 499 frvbf_model_fr550_u_idiv (SIM_CPU *cpu, const IDESC *idesc, 554 frvbf_model_fr550_u_branch (SIM_CPU *cpu, const IDESC *idesc, 604 frvbf_model_fr550_u_trap (SIM_CPU *cpu, const IDESC *idesc, 635 frvbf_model_fr550_u_check (SIM_CPU *cpu, const IDESC *idesc, 645 frvbf_model_fr550_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, 671 frvbf_model_fr550_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, 713 frvbf_model_fr550_u_gr_store (SIM_CPU *cpu, const IDESC *ides [all...] |
H A D | decode.c | 35 static IDESC frvbf_insn_data[FRVBF_INSN__MAX]; 797 /* Initialize an IDESC from the compile-time computable parts. */ 800 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 830 IDESC *id,*tabend; 833 IDESC *table = frvbf_insn_data; 835 memset (table, 0, tabsize * sizeof (IDESC)); 849 /* Link the IDESC table into the cpu. */ 853 /* Given an instruction, return a pointer to its IDESC entry. */ 855 const IDESC * 4490 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/frv/ |
H A D | profile-fr550.c | 419 frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc, 426 frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc, 461 frvbf_model_fr550_u_imul (SIM_CPU *cpu, const IDESC *idesc, 499 frvbf_model_fr550_u_idiv (SIM_CPU *cpu, const IDESC *idesc, 554 frvbf_model_fr550_u_branch (SIM_CPU *cpu, const IDESC *idesc, 604 frvbf_model_fr550_u_trap (SIM_CPU *cpu, const IDESC *idesc, 635 frvbf_model_fr550_u_check (SIM_CPU *cpu, const IDESC *idesc, 645 frvbf_model_fr550_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, 671 frvbf_model_fr550_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, 713 frvbf_model_fr550_u_gr_store (SIM_CPU *cpu, const IDESC *ides [all...] |
H A D | decode.c | 35 static IDESC frvbf_insn_data[FRVBF_INSN__MAX]; 797 /* Initialize an IDESC from the compile-time computable parts. */ 800 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 830 IDESC *id,*tabend; 833 IDESC *table = frvbf_insn_data; 835 memset (table, 0, tabsize * sizeof (IDESC)); 849 /* Link the IDESC table into the cpu. */ 853 /* Given an instruction, return a pointer to its IDESC entry. */ 855 const IDESC * 4490 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/frv/ |
H A D | profile-fr550.c | 419 frvbf_model_fr550_u_exec (SIM_CPU *cpu, const IDESC *idesc, 426 frvbf_model_fr550_u_integer (SIM_CPU *cpu, const IDESC *idesc, 461 frvbf_model_fr550_u_imul (SIM_CPU *cpu, const IDESC *idesc, 499 frvbf_model_fr550_u_idiv (SIM_CPU *cpu, const IDESC *idesc, 554 frvbf_model_fr550_u_branch (SIM_CPU *cpu, const IDESC *idesc, 604 frvbf_model_fr550_u_trap (SIM_CPU *cpu, const IDESC *idesc, 635 frvbf_model_fr550_u_check (SIM_CPU *cpu, const IDESC *idesc, 645 frvbf_model_fr550_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, 671 frvbf_model_fr550_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, 713 frvbf_model_fr550_u_gr_store (SIM_CPU *cpu, const IDESC *ides [all...] |
H A D | decode.c | 35 static IDESC frvbf_insn_data[FRVBF_INSN__MAX]; 797 /* Initialize an IDESC from the compile-time computable parts. */ 800 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) 830 IDESC *id,*tabend; 833 IDESC *table = frvbf_insn_data; 835 memset (table, 0, tabsize * sizeof (IDESC)); 849 /* Link the IDESC table into the cpu. */ 853 /* Given an instruction, return a pointer to its IDESC entry. */ 855 const IDESC * 4490 const IDESC *ides [all...] |
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/iq2000/ |
H A D | decode.h | 27 extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR, 90 extern int iq2000bf_model_iq2000_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/iq2000/ |
H A D | decode.h | 27 extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR, 90 extern int iq2000bf_model_iq2000_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/iq2000/ |
H A D | decode.h | 27 extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR, 90 extern int iq2000bf_model_iq2000_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/common/ |
H A D | cgen-cpu.h | 62 IDESC *idesc; 80 /* Function to fetch the insn data entry in the IDESC. */
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H A D | cgen-defs.h | 54 typedef struct idesc IDESC; 53 typedef struct idesc IDESC; typedef in typeref:struct:idesc
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