Searched hist:292903 (Results 1 - 6 of 6) sorted by relevance

/freebsd-11.0-release/sys/powerpc/booke/
H A Dmachdep_e500.cdiff 292903 Wed Dec 30 03:59:15 MST 2015 jhibbits Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing
H A Dlocore.Sdiff 292903 Wed Dec 30 03:59:15 MST 2015 jhibbits Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing
H A Dbooke_machdep.cdiff 292903 Wed Dec 30 03:59:15 MST 2015 jhibbits Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing
/freebsd-11.0-release/sys/powerpc/mpc85xx/
H A Dmpc85xx.cdiff 292903 Wed Dec 30 03:59:15 MST 2015 jhibbits Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing
H A Dmpc85xx.hdiff 292903 Wed Dec 30 03:59:15 MST 2015 jhibbits Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing
H A Dplatform_mpc85xx.cdiff 292903 Wed Dec 30 03:59:15 MST 2015 jhibbits Add platform support for QorIQ SoCs.

This includes the following changes:
* SMP kickoff for QorIQ (tested on P5020)
* Errata fixes for some silicon revisions
* Enables L2 (and L3 if available) caches
Obtained from: Semihalf
Sponsored by: Alex Perez/Inertial Computing

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