1236324Sraj/*- 2236324Sraj * Copyright (c) 2011-2012 Semihalf. 3236324Sraj * All rights reserved. 4236324Sraj * 5236324Sraj * Redistribution and use in source and binary forms, with or without 6236324Sraj * modification, are permitted provided that the following conditions 7236324Sraj * are met: 8236324Sraj * 1. Redistributions of source code must retain the above copyright 9236324Sraj * notice, this list of conditions and the following disclaimer. 10236324Sraj * 2. Redistributions in binary form must reproduce the above copyright 11236324Sraj * notice, this list of conditions and the following disclaimer in the 12236324Sraj * documentation and/or other materials provided with the distribution. 13236324Sraj * 14236324Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15236324Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16236324Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17236324Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18236324Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19236324Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20236324Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21236324Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22236324Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23236324Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24236324Sraj * SUCH DAMAGE. 25236324Sraj */ 26236324Sraj 27236324Sraj#include <sys/cdefs.h> 28236324Sraj__FBSDID("$FreeBSD: releng/11.0/sys/powerpc/booke/machdep_e500.c 292903 2015-12-30 03:43:25Z jhibbits $"); 29236324Sraj 30292903Sjhibbits#include <sys/cdefs.h> 31236324Sraj#include <sys/types.h> 32292903Sjhibbits#include <sys/param.h> 33292903Sjhibbits#include <sys/proc.h> 34236324Sraj#include <sys/reboot.h> 35236324Sraj 36292903Sjhibbits#include <vm/vm.h> 37292903Sjhibbits#include <vm/pmap.h> 38292903Sjhibbits 39236324Sraj#include <machine/machdep.h> 40236324Sraj 41236324Sraj#include <dev/fdt/fdt_common.h> 42236324Sraj 43236324Sraj#include <powerpc/mpc85xx/mpc85xx.h> 44236324Sraj 45236324Srajextern void dcache_enable(void); 46236324Srajextern void dcache_inval(void); 47236324Srajextern void icache_enable(void); 48236324Srajextern void icache_inval(void); 49236324Srajextern void l2cache_enable(void); 50236324Srajextern void l2cache_inval(void); 51292903Sjhibbitsextern void bpred_enable(void); 52236324Sraj 53236324Srajvoid 54236324Srajbooke_init_tlb(vm_paddr_t fdt_immr_pa) 55236324Sraj{ 56236324Sraj 57236324Sraj} 58236324Sraj 59236324Srajvoid 60236324Srajbooke_enable_l1_cache(void) 61236324Sraj{ 62236324Sraj uint32_t csr; 63236324Sraj 64236324Sraj /* Enable D-cache if applicable */ 65236324Sraj csr = mfspr(SPR_L1CSR0); 66236324Sraj if ((csr & L1CSR0_DCE) == 0) { 67236324Sraj dcache_inval(); 68236324Sraj dcache_enable(); 69236324Sraj } 70236324Sraj 71236324Sraj csr = mfspr(SPR_L1CSR0); 72236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) 73236324Sraj printf("L1 D-cache %sabled\n", 74236324Sraj (csr & L1CSR0_DCE) ? "en" : "dis"); 75236324Sraj 76236324Sraj /* Enable L1 I-cache if applicable. */ 77236324Sraj csr = mfspr(SPR_L1CSR1); 78236324Sraj if ((csr & L1CSR1_ICE) == 0) { 79236324Sraj icache_inval(); 80236324Sraj icache_enable(); 81236324Sraj } 82236324Sraj 83236324Sraj csr = mfspr(SPR_L1CSR1); 84236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) 85236324Sraj printf("L1 I-cache %sabled\n", 86236324Sraj (csr & L1CSR1_ICE) ? "en" : "dis"); 87236324Sraj} 88236324Sraj 89236324Srajvoid 90236324Srajbooke_enable_l2_cache(void) 91236324Sraj{ 92236324Sraj uint32_t csr; 93236324Sraj 94236324Sraj /* Enable L2 cache on E500mc */ 95236324Sraj if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || 96236324Sraj (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { 97236324Sraj csr = mfspr(SPR_L2CSR0); 98236324Sraj if ((csr & L2CSR0_L2E) == 0) { 99236324Sraj l2cache_inval(); 100236324Sraj l2cache_enable(); 101236324Sraj } 102236324Sraj 103236324Sraj csr = mfspr(SPR_L2CSR0); 104236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) 105236324Sraj printf("L2 cache %sabled\n", 106236324Sraj (csr & L2CSR0_L2E) ? "en" : "dis"); 107236324Sraj } 108236324Sraj} 109236324Sraj 110236324Srajvoid 111292903Sjhibbitsbooke_enable_bpred(void) 112236324Sraj{ 113292903Sjhibbits uint32_t csr; 114236324Sraj 115292903Sjhibbits bpred_enable(); 116292903Sjhibbits csr = mfspr(SPR_BUCSR); 117292903Sjhibbits if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0) 118292903Sjhibbits printf("Branch Predictor %sabled\n", 119292903Sjhibbits (csr & BUCSR_BPEN) ? "en" : "dis"); 120236324Sraj} 121236324Sraj 122236324Srajvoid 123236324Srajbooke_disable_l2_cache(void) 124236324Sraj{ 125236324Sraj} 126