Searched hist:276287 (Results 1 - 3 of 3) sorted by relevance
| /freebsd-10-stable/sys/arm/ti/ | ||
| H A D | ti_sdhci.c | diff 276287 Sat Dec 27 03:05:20 MST 2014 ian MFC r275944, r275946, r275949, r275950: Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. diff 276287 Sat Dec 27 03:05:20 MST 2014 ian MFC r275944, r275946, r275949, r275950: Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. |
| /freebsd-10-stable/sys/dev/sdhci/ | ||
| H A D | sdhci.c | diff 276287 Sat Dec 27 03:05:20 MST 2014 ian MFC r275944, r275946, r275949, r275950: Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. diff 276287 Sat Dec 27 03:05:20 MST 2014 ian MFC r275944, r275946, r275949, r275950: Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. |
| H A D | sdhci.h | diff 276287 Sat Dec 27 03:05:20 MST 2014 ian MFC r275944, r275946, r275949, r275950: Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. diff 276287 Sat Dec 27 03:05:20 MST 2014 ian MFC r275944, r275946, r275949, r275950: Add code to set and reset open-drain mode on the bus when requested. When command and data interrupts have been aggregated together, don't do the data-completed processing if a command-error interrupt is also asserted. Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around TI OMAP controllers which will return the reset-in-progress bit as zero if you read the status register too fast after setting the reset bit. |
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