1254559Sian/*- 2254559Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3254559Sian * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4254559Sian * All rights reserved. 5254559Sian * 6254559Sian * Redistribution and use in source and binary forms, with or without 7254559Sian * modification, are permitted provided that the following conditions 8254559Sian * are met: 9254559Sian * 1. Redistributions of source code must retain the above copyright 10254559Sian * notice, this list of conditions and the following disclaimer. 11254559Sian * 2. Redistributions in binary form must reproduce the above copyright 12254559Sian * notice, this list of conditions and the following disclaimer in the 13254559Sian * documentation and/or other materials provided with the distribution. 14254559Sian * 15254559Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16254559Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17254559Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18254559Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19254559Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20254559Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21254559Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22254559Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23254559Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24254559Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25254559Sian * SUCH DAMAGE. 26254559Sian * 27254559Sian */ 28254559Sian#include <sys/cdefs.h> 29254559Sian__FBSDID("$FreeBSD: stable/10/sys/arm/ti/ti_sdhci.c 343505 2019-01-27 19:05:18Z marius $"); 30254559Sian 31254559Sian#include <sys/param.h> 32254559Sian#include <sys/systm.h> 33254559Sian#include <sys/bus.h> 34254559Sian#include <sys/gpio.h> 35254559Sian#include <sys/kernel.h> 36254559Sian#include <sys/malloc.h> 37254559Sian#include <sys/module.h> 38254559Sian#include <sys/resource.h> 39254559Sian#include <sys/rman.h> 40271051Smarius#include <sys/sysctl.h> 41254559Sian#include <sys/taskqueue.h> 42254559Sian 43254559Sian#include <machine/bus.h> 44254559Sian#include <machine/resource.h> 45254559Sian#include <machine/intr.h> 46254559Sian 47254559Sian#include <dev/fdt/fdt_common.h> 48254559Sian#include <dev/ofw/ofw_bus.h> 49254559Sian#include <dev/ofw/ofw_bus_subr.h> 50254559Sian 51254559Sian#include <dev/mmc/bridge.h> 52254559Sian#include <dev/mmc/mmcreg.h> 53254559Sian#include <dev/mmc/mmcbrvar.h> 54254559Sian 55254559Sian#include <dev/sdhci/sdhci.h> 56254559Sian#include "sdhci_if.h" 57254559Sian 58254559Sian#include <arm/ti/ti_cpuid.h> 59254559Sian#include <arm/ti/ti_prcm.h> 60254559Sian#include "gpio_if.h" 61254559Sian 62254559Sianstruct ti_sdhci_softc { 63254559Sian device_t dev; 64254559Sian device_t gpio_dev; 65254559Sian struct resource * mem_res; 66254559Sian struct resource * irq_res; 67254559Sian void * intr_cookie; 68254559Sian struct sdhci_slot slot; 69254559Sian uint32_t mmchs_device_id; 70254559Sian uint32_t mmchs_reg_off; 71254559Sian uint32_t sdhci_reg_off; 72254559Sian uint32_t baseclk_hz; 73254559Sian uint32_t wp_gpio_pin; 74254559Sian uint32_t cmd_and_mode; 75254559Sian uint32_t sdhci_clkdiv; 76266751Sian boolean_t disable_highspeed; 77266751Sian boolean_t force_card_present; 78254559Sian}; 79254559Sian 80254559Sian/* 81259356Sian * Table of supported FDT compat strings. 82259356Sian * 83259356Sian * Note that "ti,mmchs" is our own invention, and should be phased out in favor 84259356Sian * of the documented names. 85259356Sian * 86259356Sian * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 87259356Sian */ 88259356Sianstatic struct ofw_compat_data compat_data[] = { 89259356Sian {"ti,omap3-hsmmc", 1}, 90259356Sian {"ti,omap4-hsmmc", 1}, 91259356Sian {"ti,mmchs", 1}, 92259356Sian {NULL, 0}, 93259356Sian}; 94259356Sian 95259356Sian/* 96254559Sian * The MMCHS hardware has a few control and status registers at the beginning of 97254559Sian * the device's memory map, followed by the standard sdhci register block. 98254559Sian * Different SoCs have the register blocks at different offsets from the 99254559Sian * beginning of the device. Define some constants to map out the registers we 100254559Sian * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 101254559Sian * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 102254559Sian */ 103254559Sian#define OMAP3_MMCHS_REG_OFFSET 0x000 104254559Sian#define OMAP4_MMCHS_REG_OFFSET 0x100 105254559Sian#define AM335X_MMCHS_REG_OFFSET 0x100 106254559Sian#define SDHCI_REG_OFFSET 0x100 107254559Sian 108254559Sian#define MMCHS_SYSCONFIG 0x010 109254559Sian#define MMCHS_SYSCONFIG_RESET (1 << 1) 110254559Sian#define MMCHS_SYSSTATUS 0x014 111266751Sian#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 112254559Sian#define MMCHS_CON 0x02C 113254559Sian#define MMCHS_CON_DW8 (1 << 5) 114254559Sian#define MMCHS_CON_DVAL_8_4MS (3 << 9) 115276287Sian#define MMCHS_CON_OD (1 << 0) 116266751Sian#define MMCHS_SYSCTL 0x12C 117266751Sian#define MMCHS_SYSCTL_CLKD_MASK 0x3FF 118266751Sian#define MMCHS_SYSCTL_CLKD_SHIFT 6 119259374Sian#define MMCHS_SD_CAPA 0x140 120259356Sian#define MMCHS_SD_CAPA_VS18 (1 << 26) 121259356Sian#define MMCHS_SD_CAPA_VS30 (1 << 25) 122259356Sian#define MMCHS_SD_CAPA_VS33 (1 << 24) 123254559Sian 124254559Sianstatic inline uint32_t 125254559Sianti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 126254559Sian{ 127254559Sian 128254559Sian return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 129254559Sian} 130254559Sian 131254559Sianstatic inline void 132254559Sianti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 133254559Sian{ 134254559Sian 135254559Sian bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 136254559Sian} 137254559Sian 138254559Sianstatic inline uint32_t 139254559SianRD4(struct ti_sdhci_softc *sc, bus_size_t off) 140254559Sian{ 141254559Sian 142254559Sian return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 143254559Sian} 144254559Sian 145254559Sianstatic inline void 146254559SianWR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 147254559Sian{ 148254559Sian 149254559Sian bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 150254559Sian} 151254559Sian 152254559Sianstatic uint8_t 153254559Sianti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 154254559Sian{ 155254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 156254559Sian 157254559Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 158254559Sian} 159254559Sian 160254559Sianstatic uint16_t 161254559Sianti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 162254559Sian{ 163254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 164254559Sian uint32_t clkdiv, val32; 165254559Sian 166254559Sian /* 167254559Sian * The MMCHS hardware has a non-standard interpretation of the sdclock 168254559Sian * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 169254559Sian * but doesn't split them into low:high fields. Instead they're a 170254559Sian * single number in the range 0..1023 and the number is exactly the 171254559Sian * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 172266751Sian * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 173254559Sian * here extracts the MMCHS representation from the hardware word, cleans 174266751Sian * those bits out, applies the 2N adjustment, and plugs the result into 175266751Sian * the bit positions for the 2.0 or 3.0 divisor in the returned register 176266751Sian * value. The ti_sdhci_write_2() routine performs the opposite 177266751Sian * transformation when the SDHCI driver writes to the register. 178254559Sian */ 179254559Sian if (off == SDHCI_CLOCK_CONTROL) { 180254559Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 181266751Sian clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 182266751Sian MMCHS_SYSCTL_CLKD_MASK) / 2; 183266751Sian val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 184266751Sian val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 185266751Sian if (slot->version >= SDHCI_SPEC_300) 186266751Sian val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 187266751Sian SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 188254559Sian return (val32 & 0xffff); 189254559Sian } 190254559Sian 191254559Sian /* 192254559Sian * Standard 32-bit handling of command and transfer mode. 193254559Sian */ 194254559Sian if (off == SDHCI_TRANSFER_MODE) { 195254559Sian return (sc->cmd_and_mode >> 16); 196254559Sian } else if (off == SDHCI_COMMAND_FLAGS) { 197254559Sian return (sc->cmd_and_mode & 0x0000ffff); 198254559Sian } 199254559Sian 200254559Sian return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 201254559Sian} 202254559Sian 203254559Sianstatic uint32_t 204254559Sianti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 205254559Sian{ 206254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 207266751Sian uint32_t val32; 208254559Sian 209266751Sian val32 = RD4(sc, off); 210266751Sian 211266751Sian /* 212266751Sian * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 213266751Sian * that flag from the returned capabilities. 214266751Sian */ 215266751Sian if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 216266751Sian val32 &= ~SDHCI_CAN_DO_HISPD; 217266751Sian 218266751Sian /* 219266751Sian * Force the card-present state if necessary. 220266751Sian */ 221266751Sian if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 222266751Sian val32 |= SDHCI_CARD_PRESENT; 223266751Sian 224266751Sian return (val32); 225254559Sian} 226254559Sian 227254559Sianstatic void 228254559Sianti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 229254559Sian uint32_t *data, bus_size_t count) 230254559Sian{ 231254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 232254559Sian 233254559Sian bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 234254559Sian} 235254559Sian 236254559Sianstatic void 237254559Sianti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 238254559Sian uint8_t val) 239254559Sian{ 240254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 241254559Sian uint32_t val32; 242254559Sian 243254559Sian val32 = RD4(sc, off & ~3); 244254559Sian val32 &= ~(0xff << (off & 3) * 8); 245254559Sian val32 |= (val << (off & 3) * 8); 246254559Sian 247254559Sian WR4(sc, off & ~3, val32); 248254559Sian} 249254559Sian 250254559Sianstatic void 251254559Sianti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 252254559Sian uint16_t val) 253254559Sian{ 254254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 255254559Sian uint32_t clkdiv, val32; 256254559Sian 257254559Sian /* 258266751Sian * Translate between the hardware and SDHCI 2.0 or 3.0 representations 259266751Sian * of the clock divisor. See the comments in ti_sdhci_read_2() for 260266751Sian * details. 261254559Sian */ 262254559Sian if (off == SDHCI_CLOCK_CONTROL) { 263254559Sian clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 264266751Sian if (slot->version >= SDHCI_SPEC_300) 265266751Sian clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 266266751Sian SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 267266751Sian clkdiv *= 2; 268266751Sian if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 269266751Sian clkdiv = MMCHS_SYSCTL_CLKD_MASK; 270254559Sian val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 271254559Sian val32 &= 0xffff0000; 272266751Sian val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 273266751Sian MMCHS_SYSCTL_CLKD_SHIFT); 274266751Sian val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 275254559Sian WR4(sc, SDHCI_CLOCK_CONTROL, val32); 276254559Sian return; 277254559Sian } 278254559Sian 279254559Sian /* 280254559Sian * Standard 32-bit handling of command and transfer mode. 281254559Sian */ 282254559Sian if (off == SDHCI_TRANSFER_MODE) { 283254559Sian sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 284254559Sian ((uint32_t)val & 0x0000ffff); 285254559Sian return; 286254559Sian } else if (off == SDHCI_COMMAND_FLAGS) { 287254559Sian sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 288254559Sian ((uint32_t)val << 16); 289254559Sian WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 290254559Sian return; 291254559Sian } 292254559Sian 293254559Sian val32 = RD4(sc, off & ~3); 294254559Sian val32 &= ~(0xffff << (off & 3) * 8); 295254559Sian val32 |= ((val & 0xffff) << (off & 3) * 8); 296254559Sian WR4(sc, off & ~3, val32); 297254559Sian} 298254559Sian 299254559Sianstatic void 300254559Sianti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 301254559Sian uint32_t val) 302254559Sian{ 303254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 304254559Sian 305254559Sian WR4(sc, off, val); 306254559Sian} 307254559Sian 308254559Sianstatic void 309254559Sianti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 310254559Sian uint32_t *data, bus_size_t count) 311254559Sian{ 312254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 313254559Sian 314254559Sian bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 315254559Sian} 316254559Sian 317254559Sianstatic void 318254559Sianti_sdhci_intr(void *arg) 319254559Sian{ 320254559Sian struct ti_sdhci_softc *sc = arg; 321254559Sian 322254559Sian sdhci_generic_intr(&sc->slot); 323254559Sian} 324254559Sian 325254559Sianstatic int 326254559Sianti_sdhci_update_ios(device_t brdev, device_t reqdev) 327254559Sian{ 328254559Sian struct ti_sdhci_softc *sc = device_get_softc(brdev); 329254559Sian struct sdhci_slot *slot; 330254559Sian struct mmc_ios *ios; 331276287Sian uint32_t val32, newval32; 332254559Sian 333254559Sian slot = device_get_ivars(reqdev); 334254559Sian ios = &slot->host.ios; 335254559Sian 336254559Sian /* 337254559Sian * There is an 8-bit-bus bit in the MMCHS control register which, when 338254559Sian * set, overrides the 1 vs 4 bit setting in the standard SDHCI 339254559Sian * registers. Set that bit first according to whether an 8-bit bus is 340254559Sian * requested, then let the standard driver handle everything else. 341254559Sian */ 342254559Sian val32 = ti_mmchs_read_4(sc, MMCHS_CON); 343276287Sian newval32 = val32; 344276287Sian 345254559Sian if (ios->bus_width == bus_width_8) 346276287Sian newval32 |= MMCHS_CON_DW8; 347254559Sian else 348276287Sian newval32 &= ~MMCHS_CON_DW8; 349254559Sian 350276287Sian if (ios->bus_mode == opendrain) 351276287Sian newval32 |= MMCHS_CON_OD; 352276287Sian else /* if (ios->bus_mode == pushpull) */ 353276287Sian newval32 &= ~MMCHS_CON_OD; 354276287Sian 355276287Sian if (newval32 != val32) 356276287Sian ti_mmchs_write_4(sc, MMCHS_CON, newval32); 357276287Sian 358254559Sian return (sdhci_generic_update_ios(brdev, reqdev)); 359254559Sian} 360254559Sian 361254559Sianstatic int 362254559Sianti_sdhci_get_ro(device_t brdev, device_t reqdev) 363254559Sian{ 364254559Sian struct ti_sdhci_softc *sc = device_get_softc(brdev); 365254559Sian unsigned int readonly = 0; 366254559Sian 367254559Sian /* If a gpio pin is configured, read it. */ 368254559Sian if (sc->gpio_dev != NULL) { 369254559Sian GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 370254559Sian } 371254559Sian 372254559Sian return (readonly); 373254559Sian} 374254559Sian 375254559Sianstatic int 376254559Sianti_sdhci_detach(device_t dev) 377254559Sian{ 378254559Sian 379254559Sian return (EBUSY); 380254559Sian} 381254559Sian 382254559Sianstatic void 383254559Sianti_sdhci_hw_init(device_t dev) 384254559Sian{ 385254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 386254559Sian clk_ident_t clk; 387259356Sian uint32_t regval; 388254559Sian unsigned long timeout; 389254559Sian 390254559Sian /* Enable the controller and interface/functional clocks */ 391254559Sian clk = MMC0_CLK + sc->mmchs_device_id; 392254559Sian if (ti_prcm_clk_enable(clk) != 0) { 393254559Sian device_printf(dev, "Error: failed to enable MMC clock\n"); 394254559Sian return; 395254559Sian } 396254559Sian 397254559Sian /* Get the frequency of the source clock */ 398254559Sian if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) { 399254559Sian device_printf(dev, "Error: failed to get source clock freq\n"); 400254559Sian return; 401254559Sian } 402254559Sian 403254559Sian /* Issue a softreset to the controller */ 404254559Sian ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 405254559Sian timeout = 1000; 406276287Sian while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 407276287Sian MMCHS_SYSSTATUS_RESETDONE)) { 408254559Sian if (--timeout == 0) { 409276287Sian device_printf(dev, 410276287Sian "Error: Controller reset operation timed out\n"); 411254559Sian break; 412254559Sian } 413254559Sian DELAY(100); 414254559Sian } 415254559Sian 416276287Sian /* 417276287Sian * Reset the command and data state machines and also other aspects of 418276287Sian * the controller such as bus clock and power. 419276287Sian * 420276287Sian * If we read the software reset register too fast after writing it we 421276287Sian * can get back a zero that means the reset hasn't started yet rather 422276287Sian * than that the reset is complete. Per TI recommendations, work around 423276287Sian * it by reading until we see the reset bit asserted, then read until 424276287Sian * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk 425276287Sian * so that the main sdhci driver uses this same logic in its resets. 426276287Sian */ 427254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 428276287Sian timeout = 10000; 429276287Sian while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 430276287Sian SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { 431254559Sian if (--timeout == 0) { 432254559Sian break; 433254559Sian } 434276287Sian DELAY(1); 435276287Sian } 436276287Sian timeout = 10000; 437276287Sian while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 438276287Sian SDHCI_RESET_ALL)) { 439276287Sian if (--timeout == 0) { 440276287Sian device_printf(dev, 441276287Sian "Error: Software reset operation timed out\n"); 442276287Sian break; 443276287Sian } 444254559Sian DELAY(100); 445254559Sian } 446254559Sian 447259356Sian /* 448259356Sian * The attach() routine has examined fdt data and set flags in 449259356Sian * slot.host.caps to reflect what voltages we can handle. Set those 450259356Sian * values in the CAPA register. The manual says that these values can 451259356Sian * only be set once, "before initialization" whatever that means, and 452259356Sian * that they survive a reset. So maybe doing this will be a no-op if 453259356Sian * u-boot has already initialized the hardware. 454259356Sian */ 455259356Sian regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 456259356Sian if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 457259356Sian regval |= MMCHS_SD_CAPA_VS18; 458259356Sian if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 459259356Sian regval |= MMCHS_SD_CAPA_VS30; 460259356Sian ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 461259356Sian 462254559Sian /* Set initial host configuration (1-bit, std speed, pwr off). */ 463254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 464254559Sian ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 465254559Sian 466254559Sian /* Set the initial controller configuration. */ 467254559Sian ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 468254559Sian} 469254559Sian 470254559Sianstatic int 471254559Sianti_sdhci_attach(device_t dev) 472254559Sian{ 473254559Sian struct ti_sdhci_softc *sc = device_get_softc(dev); 474254559Sian int rid, err; 475254559Sian pcell_t prop; 476254559Sian phandle_t node; 477254559Sian 478254559Sian sc->dev = dev; 479254559Sian 480254559Sian /* 481254559Sian * Get the MMCHS device id from FDT. If it's not there use the newbus 482254559Sian * unit number (which will work as long as the devices are in order and 483259356Sian * none are skipped in the fdt). Note that this is a property we made 484259356Sian * up and added in freebsd, it doesn't exist in the published bindings. 485254559Sian */ 486254559Sian node = ofw_bus_get_node(dev); 487254559Sian if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) { 488254559Sian sc->mmchs_device_id = device_get_unit(dev); 489254559Sian device_printf(dev, "missing mmchs-device-id attribute in FDT, " 490254559Sian "using unit number (%d)", sc->mmchs_device_id); 491254559Sian } else 492254559Sian sc->mmchs_device_id = fdt32_to_cpu(prop); 493254559Sian 494259356Sian /* 495259356Sian * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 496259356Sian * device, and only 1p8v on other devices unless an external transceiver 497259356Sian * is used. The only way we could know about a transceiver is fdt data. 498259356Sian * Note that we have to do this before calling ti_sdhci_hw_init() so 499259356Sian * that it can set the right values in the CAPA register, which can only 500259356Sian * be done once and never reset. 501259356Sian */ 502259374Sian sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 503259356Sian if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) { 504259374Sian sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 505259356Sian } 506259356Sian 507259356Sian /* 508259356Sian * See if we've got a GPIO-based write detect pin. This is not the 509259356Sian * standard documented property for this, we added it in freebsd. 510259356Sian */ 511254559Sian if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 512254559Sian sc->wp_gpio_pin = 0xffffffff; 513254559Sian else 514254559Sian sc->wp_gpio_pin = fdt32_to_cpu(prop); 515254559Sian 516254559Sian if (sc->wp_gpio_pin != 0xffffffff) { 517254559Sian sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 518254559Sian if (sc->gpio_dev == NULL) 519254559Sian device_printf(dev, "Error: No GPIO device, " 520254559Sian "Write Protect pin will not function\n"); 521254559Sian else 522254559Sian GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 523254559Sian GPIO_PIN_INPUT); 524254559Sian } 525254559Sian 526254559Sian /* 527254559Sian * Set the offset from the device's memory start to the MMCHS registers. 528266751Sian * Also for OMAP4 disable high speed mode due to erratum ID i626. 529254559Sian */ 530254559Sian if (ti_chip() == CHIP_OMAP_3) 531254559Sian sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET; 532266751Sian else if (ti_chip() == CHIP_OMAP_4) { 533254559Sian sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 534266751Sian sc->disable_highspeed = true; 535266751Sian } else if (ti_chip() == CHIP_AM335X) 536254559Sian sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 537254559Sian else 538254559Sian panic("Unknown OMAP device\n"); 539254559Sian 540254559Sian /* 541254559Sian * The standard SDHCI registers are at a fixed offset (the same on all 542254559Sian * SoCs) beyond the MMCHS registers. 543254559Sian */ 544254559Sian sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 545254559Sian 546254559Sian /* Resource setup. */ 547254559Sian rid = 0; 548254559Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 549254559Sian RF_ACTIVE); 550254559Sian if (!sc->mem_res) { 551254559Sian device_printf(dev, "cannot allocate memory window\n"); 552254559Sian err = ENXIO; 553254559Sian goto fail; 554254559Sian } 555254559Sian 556254559Sian rid = 0; 557254559Sian sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 558254559Sian RF_ACTIVE); 559254559Sian if (!sc->irq_res) { 560254559Sian device_printf(dev, "cannot allocate interrupt\n"); 561254559Sian err = ENXIO; 562254559Sian goto fail; 563254559Sian } 564254559Sian 565254559Sian if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 566254559Sian NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 567254559Sian device_printf(dev, "cannot setup interrupt handler\n"); 568254559Sian err = ENXIO; 569254559Sian goto fail; 570254559Sian } 571254559Sian 572254559Sian /* Initialise the MMCHS hardware. */ 573254559Sian ti_sdhci_hw_init(dev); 574254559Sian 575254559Sian /* 576254559Sian * The capabilities register can only express base clock frequencies in 577254559Sian * the range of 0-63MHz for a v2.0 controller. Since our clock runs 578254559Sian * faster than that, the hardware sets the frequency to zero in the 579254559Sian * register. When the register contains zero, the sdhci driver expects 580254559Sian * slot.max_clk to already have the right value in it. 581254559Sian */ 582254559Sian sc->slot.max_clk = sc->baseclk_hz; 583254559Sian 584254559Sian /* 585254559Sian * The MMCHS timeout counter is based on the output sdclock. Tell the 586254559Sian * sdhci driver to recalculate the timeout clock whenever the output 587254559Sian * sdclock frequency changes. 588254559Sian */ 589254559Sian sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 590254559Sian 591254559Sian /* 592254559Sian * The MMCHS hardware shifts the 136-bit response data (in violation of 593254559Sian * the spec), so tell the sdhci driver not to do the same in software. 594254559Sian */ 595254559Sian sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 596254559Sian 597254559Sian /* 598276287Sian * Reset bits are broken, have to wait to see the bits asserted 599276287Sian * before waiting to see them de-asserted. 600276287Sian */ 601276287Sian sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; 602318198Smarius 603318198Smarius /* 604318198Smarius * The controller waits for busy responses. 605318198Smarius */ 606318198Smarius sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY; 607276287Sian 608276287Sian /* 609254559Sian * DMA is not really broken, I just haven't implemented it yet. 610254559Sian */ 611254559Sian sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 612254559Sian 613259356Sian /* 614259356Sian * Set up the hardware and go. Note that this sets many of the 615259356Sian * slot.host.* fields, so we have to do this before overriding any of 616259356Sian * those values based on fdt data, below. 617259356Sian */ 618254559Sian sdhci_init_slot(dev, &sc->slot, 0); 619254559Sian 620254559Sian /* 621259356Sian * The SDHCI controller doesn't realize it, but we can support 8-bit 622259356Sian * even though we're not a v3.0 controller. If there's an fdt bus-width 623259356Sian * property, honor it. 624254559Sian */ 625259356Sian if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 626259356Sian sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 627259356Sian MMC_CAP_8_BIT_DATA); 628259356Sian switch (prop) { 629259356Sian case 8: 630259356Sian sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 631259356Sian /* FALLTHROUGH */ 632259356Sian case 4: 633259356Sian sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 634259356Sian break; 635259356Sian case 1: 636259356Sian break; 637259356Sian default: 638259356Sian device_printf(dev, "Bad bus-width value %u\n", prop); 639259356Sian break; 640259356Sian } 641259356Sian } 642254559Sian 643266751Sian /* 644266751Sian * If the slot is flagged with the non-removable property, set our flag 645266751Sian * to always force the SDHCI_CARD_PRESENT bit on. 646266751Sian */ 647266751Sian node = ofw_bus_get_node(dev); 648266751Sian if (OF_hasprop(node, "non-removable")) 649266751Sian sc->force_card_present = true; 650266751Sian 651254559Sian bus_generic_probe(dev); 652254559Sian bus_generic_attach(dev); 653254559Sian 654254559Sian sdhci_start_slot(&sc->slot); 655254559Sian 656254559Sian return (0); 657254559Sian 658254559Sianfail: 659254559Sian if (sc->intr_cookie) 660254559Sian bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 661254559Sian if (sc->irq_res) 662254559Sian bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 663254559Sian if (sc->mem_res) 664254559Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 665254559Sian 666254559Sian return (err); 667254559Sian} 668254559Sian 669254559Sianstatic int 670254559Sianti_sdhci_probe(device_t dev) 671254559Sian{ 672254559Sian 673266152Sian if (!ofw_bus_status_okay(dev)) 674266152Sian return (ENXIO); 675266152Sian 676259356Sian if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 677259356Sian device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 678259356Sian return (BUS_PROBE_DEFAULT); 679254559Sian } 680254559Sian 681259356Sian return (ENXIO); 682254559Sian} 683254559Sian 684254559Sianstatic device_method_t ti_sdhci_methods[] = { 685254559Sian /* Device interface */ 686254559Sian DEVMETHOD(device_probe, ti_sdhci_probe), 687254559Sian DEVMETHOD(device_attach, ti_sdhci_attach), 688254559Sian DEVMETHOD(device_detach, ti_sdhci_detach), 689254559Sian 690254559Sian /* Bus interface */ 691254559Sian DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 692254559Sian DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 693254559Sian 694254559Sian /* MMC bridge interface */ 695254559Sian DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 696254559Sian DEVMETHOD(mmcbr_request, sdhci_generic_request), 697254559Sian DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 698254559Sian DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 699254559Sian DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 700254559Sian 701254559Sian /* SDHCI registers accessors */ 702254559Sian DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 703254559Sian DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 704254559Sian DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 705254559Sian DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 706254559Sian DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 707254559Sian DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 708254559Sian DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 709254559Sian DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 710254559Sian 711254559Sian DEVMETHOD_END 712254559Sian}; 713254559Sian 714254559Sianstatic devclass_t ti_sdhci_devclass; 715254559Sian 716254559Sianstatic driver_t ti_sdhci_driver = { 717254559Sian "sdhci_ti", 718254559Sian ti_sdhci_methods, 719254559Sian sizeof(struct ti_sdhci_softc), 720254559Sian}; 721254559Sian 722318198SmariusDRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL, 723318198Smarius NULL); 724343505SmariusSDHCI_DEPEND(sdhci_ti); 725318198SmariusMMC_DECLARE_BRIDGE(sdhci_ti); 726