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/freebsd-10.0-release/sys/mips/atheros/
H A Dar71xx_cpudef.hdiff 233081 Sat Mar 17 05:36:56 MDT 2012 adrian Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.
H A Dar724x_chip.cdiff 233081 Sat Mar 17 05:36:56 MDT 2012 adrian Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.
H A Dar91xx_chip.cdiff 233081 Sat Mar 17 05:36:56 MDT 2012 adrian Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.
H A Dar71xx_chip.cdiff 233081 Sat Mar 17 05:36:56 MDT 2012 adrian Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.
H A Dar71xxreg.hdiff 233081 Sat Mar 17 05:36:56 MDT 2012 adrian Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.

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