- Copy stable/10 (r259064) to releng/10.0 as part of the
10.0-RELEASE cycle.
- Update __FreeBSD_version [1]
- Set branch name to -RC1

[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so
start releng/10.0 at '100' so the branch is started with
a value ending in zero.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add some missing AR934x register definitions.

These are needed for ethernet bootstrap.

Approved by: re@ (gjb)

Add a missing newline.

Introduce an enum which encapsulates the PHY interface types that can be
configured.

Add in the MII configuration parameters for the AR71xx.

Obtained from: Linux/OpenWRT

Break out the arge MDIO bus code into an optional argemdio device.

This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
and call it early during MDIO bus attach. It's required for
correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
MDIO bus. The initial code mapped miibus0(arge0) and miibus1(arge1)
MII register operations to the MII0 (arge0) register space. The
AR724x (and later, upcoming chipsets) have two MDIO busses and
the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
PHY will still be enumerated), multiphy setups may be quite wrong.
I'll go and fix these so they still have a chance of working, at least.
until the switch PHY support appears in -HEAD.

Submitted by: Stefan Bethke <stb@lassitu.de>

Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.

- Fix values of CS1_EN and CS2_EN flags
- Unbreak kernel build by fixing naming convention of
GPIO_FUNC flags

Spotted by: Luiz Otavio O Souza, Andrew Thompson

AR71XX_GPIO_* defines were introduced by adrian@ a while ago,
remove duplicated.

Add AR71XX GPIO bus driver.

Implement PLL generalisation in preparation for use in if_arge.

* Add a function to write to the relevant PLL register
* Break out the PLL configuration for the AR71XX into the CPU ops,
lifted from if_arge.c.
* Add the AR91XX PLL configuration ops, using the AR91XX register
definitions.

Add some initial AR724X chipset support.

This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.

Add initial Atheros AR91XX support.

This works well enough to bring a system up to single-user mode
using an MDROOT.

Known Issues:

* The EHCI USB doesn't currently work and will panic the kernel during
attach.
* The onboard ethernet won't work until the PLL routines have been
fleshed out and shoe-horned into if_arge.
* The WMAC device glue (and quite likely the if_ath support)
hasn't yet been implemented.

Preparation work for supporting the AR91xx and AR724x.

* Implement a SoC probe function, from Linux, which determines the
SoC family, type and revision. This only probes the AR71xx series
SoC and (currently) panics on others.

* Migrate some of the AR71XX specific hardware init (USB device, determining
system frequencies) into using the cpuops introduced in an earlier commit.
Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
Ethernet PLL setup, other things I've likely missed) will be introduced in
subsequent commits.

Reviewed by: imp@
Obtained from: (partially) Linux

Add a DDR flush function, inspired by both Linux and if_arge.c.

Fix the CS line definitions. These bits are for the CS2/CS1 lines
rather than CS1/CS0.

This has been tested on the Ubiqiti Routerstation Pro board.

Comment about the shared pins I know about.

AR71XX GPIO register definitions.

Reviewed by: gonzo@

Define DMA_RX_STATUS_OVERFLOW with correct value.

The RX overflow is reported in bit 2 on real hardware and Linux driver
for the same device already has this defined correctly.
This fixes frequent interrupt storms seen on RouterStation Pro boards.

Discussed with: gonzo

- Remove unnecessary register writes in activate_device
and deactivate_device
- Save state before attaching driver and restore it when
detaching
- Clear CLK bit after last bit of byte has been sent over
the bus providing falling edge for last byte in transfer
- Fix several places where CS0 was always assumed
- Add $FreeBSD$ to ar71xxreg.h

Set the svn:eol-style = native and svn:mime-type = text/plain
properties on all files in this tree.

Submitted by: rpaulo@

Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.

Submitted by: rpaulo@

Merge from projects/mips to head by hand:

Merge support files for the Atheros AR71xx (and soon AR9xxx)
processors, except files from sys/conf and sys/mips/conf. This work
was done primarily by Olecksandr Tymoshenko and works on the
RouterStation and RouterStation PRO. Other AR71xx-based boards have
been reported as working as well (RouterBoard, for example).

- Access to all 5 PHYs goes through registers in MAC0 memory
space, rewrite miibus accessors respectively

- Fix CPU divisor mask

Repored by: Luiz Otavio O Souza

- Move CPU/AHB frequency calculations to functions to
prevent code duplication

- Fix PCI routing code

- Add polling support
- Get rid of arge_fix_chain, use m_defrag like if_vr
- Rework interrupt handling routine to avoid race that lead
to disabling RX interrupts
- Enable full duplex if requested
- Properly set station MAC address
- Slightly optimize RX loop
- Initialize FILTERMATCH and FILTERMASK registers as linux driver does

- Add definitions for PLL CPU Config register fields

- Add SPI-related registers

- Add interrupt handling for AR71XX PCI bridge

- Add APB base and size for memory rman in apb

- Revert changes accidentally killed by merge operation

- Add USB-related registers

- Add PLL, reset, ethernet and DMA registers/values

- Rename RESET-related registers
- Add PCI registers

- Change register/bitnumber/masks naming convention (again)
o For register names use AR71XX_REGISTER_NAME (prefix varies depending
on platform AR71XX/AR91XX/... Yes, let's hope other families are
on their way to tree, they call it positive thinking)
o For bit number use REGISTER_NAME_FIELD_NAME
o For field mask use REGISTER_NAME_FIELD_NAME_MASK

- Use more generic prefix for register names (ATH instead of AR71XX

- Use more generic name for atheros-based devices subdirectory. Keep old
naming scheme for files until we'll figure out common parts.

Suggested by: imp@

- First bits of Atheros' AR71XX port. Only UART supported ATM.