Searched defs:src2 (Results 1 - 25 of 30) sorted by path

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/openjdk10/hotspot/src/cpu/aarch64/vm/
H A DmacroAssembler_aarch64.hpp1251 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { argument
/openjdk10/hotspot/src/cpu/ppc/vm/
H A DmacroAssembler_ppc.cpp5030 add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) argument
/openjdk10/hotspot/src/cpu/s390/vm/
H A Dassembler_s390.inline.hpp436 inline void Assembler::z_nc(Address dst, int64_t len, Address src2) { assert(!dst.has_index() && !src2.has_index(), "Cannot encode index"); z_nc(dst.disp12(), len-1, dst.base(), src2.disp12(), src2.base()); } argument
437 inline void Assembler::z_oc(Address dst, int64_t len, Address src2) { assert(!dst.has_index() && !src2.has_index(), "Cannot encode index"); z_oc(dst.disp12(), len-1, dst.base(), src2.disp12(), src2.base()); } argument
438 inline void Assembler::z_xc(Address dst, int64_t len, Address src2) { assert(!dst.has_index() && !src2 argument
[all...]
/openjdk10/hotspot/src/cpu/x86/vm/
H A Dassembler_x86.cpp1388 void Assembler::andnl(Register dst, Register src1, Register src2) { argument
1396 void Assembler::andnl(Register dst, Register src1, Address src2) { argument
2316 void Assembler::kortestbl(KRegister src1, KRegister src2) { argument
2325 void Assembler::kortestwl(KRegister src1, KRegister src2) { argument
2334 void Assembler::kortestdl(KRegister src1, KRegister src2) { argument
2343 kortestql(KRegister src1, KRegister src2) argument
2352 ktestql(KRegister src1, KRegister src2) argument
2360 ktestq(KRegister src1, KRegister src2) argument
2368 ktestd(KRegister src1, KRegister src2) argument
4811 vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) argument
4819 vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) argument
5095 vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) argument
5103 vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) argument
5111 vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) argument
5121 vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) argument
7423 blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) argument
7443 shlxl(Register dst, Register src1, Register src2) argument
7451 shlxq(Register dst, Register src1, Register src2) argument
7986 andnq(Register dst, Register src1, Register src2) argument
7994 andnq(Register dst, Register src1, Address src2) argument
[all...]
H A DmacroAssembler_x86.cpp560 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { argument
2683 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { argument
2697 cmp32(Register src1, Address src2) argument
2755 cmpptr(Register src1, AddressLiteral src2) argument
2775 cmpptr(Address src1, AddressLiteral src2) argument
3359 store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) argument
6680 cmp_heap_oop(Register src1, Address src2, Register tmp) argument
8980 add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) argument
[all...]
H A DmacroAssembler_x86.hpp736 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } argument
761 cmpptr(Register src1, Register src2) argument
762 cmpptr(Register src1, Address src2) argument
765 cmpptr(Register src1, int32_t src2) argument
766 cmpptr(Address src1, int32_t src2) argument
808 xchgptr(Register src1, Register src2) argument
809 xchgptr(Register src1, Address src2) argument
811 xaddptr(Address src1, Register src2) argument
[all...]
/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64.test/src/org/graalvm/compiler/asm/aarch64/test/
H A DTestProtectedAssembler.java224 protected void extr(int size, Register dst, Register src1, Register src2, int lsb) { argument
229 public void adds(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) { argument
234 public void subs(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) { argument
239 protected void add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) { argument
244 protected void sub(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) { argument
249 add(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
254 adds(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
259 sub(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
264 subs(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
269 and(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
274 ands(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
279 bic(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
284 bics(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
289 eon(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
294 eor(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
299 orr(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
304 orn(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
309 asr(int size, Register dst, Register src1, Register src2) argument
314 lsl(int size, Register dst, Register src1, Register src2) argument
319 lsr(int size, Register dst, Register src1, Register src2) argument
324 ror(int size, Register dst, Register src1, Register src2) argument
349 csel(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
354 csneg(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
359 csinc(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
364 madd(int size, Register dst, Register src1, Register src2, Register src3) argument
369 msub(int size, Register dst, Register src1, Register src2, Register src3) argument
374 sdiv(int size, Register dst, Register src1, Register src2) argument
379 udiv(int size, Register dst, Register src1, Register src2) argument
449 fadd(int size, Register dst, Register src1, Register src2) argument
454 fsub(int size, Register dst, Register src1, Register src2) argument
459 fmul(int size, Register dst, Register src1, Register src2) argument
464 fdiv(int size, Register dst, Register src1, Register src2) argument
469 fmadd(int size, Register dst, Register src1, Register src2, Register src3) argument
474 fmsub(int size, Register dst, Register src1, Register src2, Register src3) argument
479 fcmp(int size, Register src1, Register src2) argument
484 fccmp(int size, Register src1, Register src2, int uimm4, ConditionFlag condition) argument
494 fcsel(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
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/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/
H A DAArch64Assembler.java1628 protected void extr(int size, Register dst, Register src1, Register src2, int lsb) { argument
1650 protected void add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) { argument
1664 adds(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) argument
1678 sub(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) argument
1692 subs(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) argument
1696 addSubShiftedInstruction(Instruction instr, Register dst, Register src1, Register src2, ShiftType shiftType, int imm, InstructionType type) argument
1713 add(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
1730 adds(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
1747 sub(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
1764 subs(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) argument
1771 addSubExtendedInstruction(Instruction instr, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt, InstructionType type) argument
1787 and(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1801 ands(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1815 bic(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1829 bics(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1843 eon(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1857 eor(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1871 orr(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1885 orn(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
1889 logicalRegInstruction(Instruction instr, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt, InstructionType type) argument
1906 asr(int size, Register dst, Register src1, Register src2) argument
1918 lsl(int size, Register dst, Register src1, Register src2) argument
1930 lsr(int size, Register dst, Register src1, Register src2) argument
1942 ror(int size, Register dst, Register src1, Register src2) argument
2010 csel(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
2023 csneg(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
2036 csinc(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
2040 conditionalSelectInstruction(Instruction instr, Register dst, Register src1, Register src2, ConditionFlag condition, InstructionType type) argument
2058 madd(int size, Register dst, Register src1, Register src2, Register src3) argument
2071 msub(int size, Register dst, Register src1, Register src2, Register src3) argument
2082 smulh(Register dst, Register src1, Register src2) argument
2096 umulh(Register dst, Register src1, Register src2) argument
2111 umaddl(Register dst, Register src1, Register src2, Register src3) argument
2127 smaddl(Register dst, Register src1, Register src2, Register src3) argument
2135 mulInstruction(Instruction instr, Register dst, Register src1, Register src2, Register src3, InstructionType type) argument
2151 sdiv(int size, Register dst, Register src1, Register src2) argument
2163 udiv(int size, Register dst, Register src1, Register src2) argument
2171 dataProcessing2SourceOp(Instruction instr, Register dst, Register src1, Register src2, InstructionType type) argument
2451 fadd(int size, Register dst, Register src1, Register src2) argument
2463 fsub(int size, Register dst, Register src1, Register src2) argument
2475 fmul(int size, Register dst, Register src1, Register src2) argument
2487 fdiv(int size, Register dst, Register src1, Register src2) argument
2491 fpDataProcessing2Source(Instruction instr, Register dst, Register src1, Register src2, InstructionType type) argument
2509 fmadd(int size, Register dst, Register src1, Register src2, Register src3) argument
2522 fmsub(int size, Register dst, Register src1, Register src2, Register src3) argument
2526 fpDataProcessing3Source(Instruction instr, Register dst, Register src1, Register src2, Register src3, InstructionType type) argument
2543 fcmp(int size, Register src1, Register src2) argument
2559 fccmp(int size, Register src1, Register src2, int uimm4, ConditionFlag condition) argument
2590 fcsel(int size, Register dst, Register src1, Register src2, ConditionFlag condition) argument
[all...]
H A DAArch64MacroAssembler.java517 public void add(int size, Register dst, Register src1, Register src2) { argument
533 public void adds(int size, Register dst, Register src1, Register src2) { argument
549 subs(int size, Register dst, Register src1, Register src2) argument
565 sub(int size, Register dst, Register src1, Register src2) argument
584 add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
600 sub(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) argument
714 mul(int size, Register dst, Register src1, Register src2) argument
726 umulh(int size, Register dst, Register src1, Register src2) argument
747 smulh(int size, Register dst, Register src1, Register src2) argument
940 and(int size, Register dst, Register src1, Register src2) argument
952 eor(int size, Register dst, Register src1, Register src2) argument
964 or(int size, Register dst, Register src1, Register src2) argument
[all...]
/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/
H A DAMD64MacroAssembler.java139 public final void cmpptr(Register src1, Register src2) { argument
143 public final void cmpptr(Register src1, AMD64Address src2) { argument
/openjdk10/hotspot/src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.lir.aarch64/src/org/graalvm/compiler/lir/aarch64/
H A DAArch64ArithmeticOp.java362 @Use(REG) protected AllocatableValue src2; field in class:AArch64ArithmeticOp.AddSubShiftOp
369 AddSubShiftOp(AArch64ArithmeticOp op, AllocatableValue result, AllocatableValue src1, AllocatableValue src2, AArch64MacroAssembler.ShiftType shiftType, int shiftAmt) argument
400 @Use(REG) protected AllocatableValue src2; field in class:AArch64ArithmeticOp.ExtendedAddShiftOp
410 ExtendedAddShiftOp(AllocatableValue result, AllocatableValue src1, AllocatableValue src2, AArch64Assembler.ExtendType extendType, int shiftAmt) argument
[all...]
/openjdk10/hotspot/src/share/vm/c1/
H A Dc1_LIR.hpp2141 void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) { argument
/openjdk10/hotspot/src/share/vm/opto/
H A Dsuperword.cpp2345 Node* src2 = vector_opd(p, 3); //3=CMoveNode::IfTrue local
/openjdk10/hotspot/test/compiler/codegen/
H A DBMI1.java250 static int andnl(int src1, int src2) { argument
254 static long andnq(long src1, long src2) { argument
258 static int andnl(int src1, MemI src2) { argument
262 andnq(long src1, MemL src2) argument
[all...]
/openjdk10/hotspot/test/compiler/intrinsics/bmi/
H A DTestAndnI.java60 public int intExpr(int src1, int src2) { argument
64 public int intExpr(int src1, Expr.MemI src2) { argument
72 public int intExpr(Expr.MemI src1, int src2) { argument
80 public int intExpr(Expr.MemI src1, Expr.MemI src2) { argument
91 intExpr(int src1, int src2) argument
95 intExpr(int src1, Expr.MemI src2) argument
103 intExpr(Expr.MemI src1, int src2) argument
111 intExpr(Expr.MemI src1, Expr.MemI src2) argument
[all...]
H A DTestAndnL.java62 public long longExpr(long src1, long src2) { argument
66 public long longExpr(long src1, Expr.MemL src2) { argument
74 public long longExpr(Expr.MemL src1, long src2) { argument
82 public long longExpr(Expr.MemL src1, Expr.MemL src2) { argument
95 longExpr(long src1, long src2) argument
99 longExpr(long src1, Expr.MemL src2) argument
107 longExpr(Expr.MemL src1, long src2) argument
115 longExpr(Expr.MemL src1, Expr.MemL src2) argument
[all...]
/openjdk10/hotspot/test/compiler/intrinsics/unsafe/
H A DTestUnsafeUnalignedMismatchedAccesses.java105 static void test8(int[] src1, int[] src2, int[] dst) { argument
/openjdk10/hotspot/test/compiler/loopopts/superword/
H A DTestVectorizationWithInvariant.java69 public static void copyByteToChar(byte[] src1, byte[] src2, char[] dst, int off) { argument
/openjdk10/hotspot/test/compiler/runtime/
H A DTest6892265.java37 static int[] src2 = new int[NCOPY]; field in class:Test6892265
/openjdk10/jaxws/src/java.xml.bind/share/classes/com/sun/xml/internal/bind/v2/runtime/
H A DIllegalAnnotationException.java62 public IllegalAnnotationException(String message, Locatable src1, Locatable src2) { argument
67 public IllegalAnnotationException(String message, Annotation src1, Annotation src2) { argument
71 public IllegalAnnotationException(String message, Annotation src1, Locatable src2) { argument
/openjdk10/jdk/src/java.desktop/share/classes/java/awt/geom/
H A DRectangle2D.java732 intersect(Rectangle2D src1, Rectangle2D src2, Rectangle2D dest) argument
771 union(Rectangle2D src1, Rectangle2D src2, Rectangle2D dest) argument
[all...]
/openjdk10/jdk/src/java.desktop/share/classes/sun/java2d/
H A DSunCompositeContext.java91 public void compose(Raster src1, Raster src2, WritableRaster dst) { argument
/openjdk10/jdk/src/java.desktop/share/native/libmlib_image/
H A Dmlib_ImageConvMxN_Fp.c169 const mlib_f32 *src2 = src + 2 * nch; local
195 const mlib_f32 *src2 = src + 2 * nch; local
218 const mlib_f32 *src2 = src + 2 * nch; local
556 const mlib_d64 *src2 = src + 2 * nch; local
582 const mlib_d64 *src2 = src + 2 * nch; local
606 const mlib_d64 *src2 = src + 2 * nch; local
[all...]
H A Dmlib_ImageConvMxN_ext.c135 const mlib_s32 *src2 = src + 2 * nch; local
/openjdk10/jdk/src/java.desktop/share/native/libsplashscreen/
H A Dsplashscreen_gfx_impl.c188 rgbquad_t src2 = getRGBA(pSrc2, srcFormat); local

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