Searched defs:regPWRSEQ0_BL_PWM_CNTL_BASE_IDX (Results 1 - 8 of 8) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h7169 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 macro
H A Ddpcs_4_2_0_offset.h87 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 macro
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H A Ddpcs_4_2_3_offset.h91 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 macro
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H A Ddpcs_4_2_2_offset.h74 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 macro
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_6_offset.h13018 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX macro
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H A Ddcn_3_1_4_offset.h11535 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX macro
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H A Ddcn_3_1_5_offset.h12287 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX macro
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H A Ddcn_3_1_2_offset.h12422 #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX macro
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