Searched defs:parent_name (Results 151 - 175 of 198) sorted by relevance

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/linux-master/drivers/clk/mvebu/
H A Dcp110-system-controller.c155 cp110_register_gate(const char *name, const char *parent_name, struct regmap *regmap, u8 bit_idx) argument
H A Dap-cpu-clk.c288 const char *parent_name; local
/linux-master/drivers/clk/davinci/
H A Dda8xx-cfgchip.c92 const char *parent_name; local
H A Dpsc.c233 davinci_lpsc_clk_register(struct device *dev, const char *name, const char *parent_name, struct regmap *regmap, u32 md, u32 pd, u32 flags) argument
H A Dpll.c233 davinci_pll_div_register(struct device *dev, const char *name, const char *parent_name, void __iomem *reg, bool fixed, u32 flags) argument
365 davinci_pll_clk_register(struct device *dev, const struct davinci_pll_clk_info *info, const char *parent_name, void __iomem *base, struct regmap *cfgchip) argument
753 const char *parent_name; local
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/linux-master/fs/xfs/
H A Dxfs_sysfs.c669 xfs_error_sysfs_init_class( struct xfs_mount *mp, int class, const char *parent_name, struct xfs_kobj *parent_kobj, const struct xfs_error_init init[]) argument
/linux-master/drivers/clk/samsung/
H A Dclk-cpu.c649 const char *parent_name; local
H A Dclk.h64 const char *parent_name; member in struct:samsung_fixed_rate_clock
90 const char *parent_name; member in struct:samsung_fixed_factor_clock
171 const char *parent_name; member in struct:samsung_div_clock
215 const char *parent_name; member in struct:samsung_gate_clock
262 const char *parent_name; member in struct:samsung_pll_clock
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/linux-master/drivers/clk/
H A Dclk-ast2600.c424 aspeed_g6_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, u8 clk_gate_flags, spinlock_t *lock) argument
H A Dclk-milbeaut.c71 const char *parent_name; member in struct:m10v_clk_div_factors
82 const char *parent_name; member in struct:m10v_clk_div_fixed_data
566 const char *parent_name; local
457 m10v_clk_hw_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock, void __iomem *write_valid_reg) argument
527 m10v_reg_fixed_pre(const struct m10v_clk_div_fixed_data *factors, struct clk_hw_onecell_data *clk_data, const char *parent_name) argument
612 const char *parent_name; local
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H A Dclk-npcm7xx.c154 const char *parent_name; member in struct:npcm7xx_clk_div_data
168 const char *parent_name; member in struct:npcm7xx_clk_pll_data
69 npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, const char *parent_name, unsigned long flags) argument
H A Dclk-cdce925.c613 const char *parent_name; local
/linux-master/drivers/clk/imx/
H A Dclk-scu.c865 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name, argument
/linux-master/drivers/clk/hisilicon/
H A Dclk-hi3559a.c28 const char *parent_name; member in struct:hi3559av100_pll_clock
/linux-master/drivers/clk/renesas/
H A Drcar-gen4-cpg.c141 cpg_pll_clk_register(const char *name, const char *parent_name, void __iomem *base, unsigned int cr0_offset, unsigned int cr1_offset, unsigned int index) argument
288 cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, unsigned int offset) argument
H A Dr9a06g032-clocks.c877 r9a06g032_register_gate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument
1048 r9a06g032_register_div(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument
1133 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument
1223 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, struct regbit sel) argument
1329 const char *parent_name = d->source ? local
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/linux-master/drivers/base/
H A Dswnode.c658 const char *parent_name = swnode->parent->node->name; local
/linux-master/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c581 const char *parent_name; local
/linux-master/drivers/clk/sifive/
H A Dsifive-prci.h265 const char *parent_name; member in struct:__prci_clock
/linux-master/drivers/clk/st/
H A Dclkgen-pll.c644 static struct clk * __init clkgen_pll_register(const char *parent_name, argument
699 static struct clk * __init clkgen_odf_register(const char *parent_name, argument
754 const char *parent_name, *pll_name; local
H A Dclkgen-fsyn.c443 st_clk_register_quadfs_pll( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, spinlock_t *lock) argument
881 st_clk_register_quadfs_fsynth( const char *name, const char *parent_name, struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, unsigned long flags, spinlock_t *lock) argument
/linux-master/drivers/media/cec/platform/meson/
H A Dao-cec-g12a.c338 const char *parent_name; local
/linux-master/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c223 mpc512x_clk_factor( const char *name, const char *parent_name, int mul, int div) argument
234 mpc512x_clk_divider( const char *name, const char *parent_name, u8 clkflags, u32 __iomem *reg, u8 pos, u8 len, int divflags) argument
243 mpc512x_clk_divtable( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos, u8 len, const struct clk_div_table *divtab) argument
256 mpc512x_clk_gated( const char *name, const char *parent_name, u32 __iomem *reg, u8 pos) argument
/linux-master/drivers/peci/controller/
H A Dpeci-aspeed.c414 const char *parent_name; local
/linux-master/arch/mips/alchemy/common/
H A Dclock.c150 static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name, argument
240 static struct clk __init *alchemy_clk_setup_aux(const char *parent_name, argument

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