Searched defs:enb (Results 1 - 7 of 7) sorted by relevance

/freebsd-9.3-release/sys/contrib/octeon-sdk/
H A Dcvmx-fpa-defs.h287 uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers member in struct:cvmx_fpa_ctl_status::cvmx_fpa_ctl_status_s
320 uint64_t enb : 1; /**< Must be set to 1 AFTER writing all config registers member in struct:cvmx_fpa_ctl_status::cvmx_fpa_ctl_status_cn30xx
H A Dcvmx-ipd-defs.h1768 uint64_t enb : 64; /**< Enable bits. */ member in struct:cvmx_ipd_port_qos_int_enbx::cvmx_ipd_port_qos_int_enbx_s
H A Dcvmx-npi-defs.h4371 uint64_t enb : 4; /**< Enables port level backpressure from the IPD. */ member in struct:cvmx_npi_port_bp_control::cvmx_npi_port_bp_control_s
H A Dcvmx-pci-defs.h4392 uint64_t enb : 1; /**< Enable the use of the Timeout function. */ member in struct:cvmx_pci_read_timeout::cvmx_pci_read_timeout_s
H A Dcvmx-npei-defs.h5572 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV0. */ member in struct:cvmx_npei_msi_enb0::cvmx_npei_msi_enb0_s
5597 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV1. */ member in struct:cvmx_npei_msi_enb1::cvmx_npei_msi_enb1_s
5622 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV2. */ member in struct:cvmx_npei_msi_enb2::cvmx_npei_msi_enb2_s
5647 uint64_t enb : 64; /**< Enables bit [63:0] of NPEI_MSI_RCV3. */ member in struct:cvmx_npei_msi_enb3::cvmx_npei_msi_enb3_s
6837 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding member in struct:cvmx_npei_pkt_instr_enb::cvmx_npei_pkt_instr_enb_s
7010 uint64_t enb : 32; /**< When asserted '1' the vector bit cooresponding member in struct:cvmx_npei_pkt_out_enb::cvmx_npei_pkt_out_enb_s
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H A Dcvmx-pcieepx-defs.h1325 uint32_t enb : 1; /**< Bar Enable member in struct:cvmx_pcieepx_cfg004_mask::cvmx_pcieepx_cfg004_mask_s
1457 uint32_t enb : 1; /**< Bar Enable member in struct:cvmx_pcieepx_cfg006_mask::cvmx_pcieepx_cfg006_mask_s
1587 uint32_t enb : 1; /**< Bar Enable member in struct:cvmx_pcieepx_cfg008_mask::cvmx_pcieepx_cfg008_mask_s
1781 uint32_t enb : 1; /**< Bar Enable NS member in struct:cvmx_pcieepx_cfg012_mask::cvmx_pcieepx_cfg012_mask_s
H A Dcvmx-sli-defs.h2064 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV0. */ member in struct:cvmx_sli_msi_enb0::cvmx_sli_msi_enb0_s
2087 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV1. */ member in struct:cvmx_sli_msi_enb1::cvmx_sli_msi_enb1_s
2110 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV2. */ member in struct:cvmx_sli_msi_enb2::cvmx_sli_msi_enb2_s
2133 uint64_t enb : 64; /**< Enables bit [63:0] of SLI_MSI_RCV3. */ member in struct:cvmx_sli_msi_enb3::cvmx_sli_msi_enb3_s
3412 uint64_t enb : 32; /**< When ENB<i>=1, instruction input ring i is enabled. */ member in struct:cvmx_sli_pkt_instr_enb::cvmx_sli_pkt_instr_enb_s
3585 uint64_t enb : 32; /**< When ENB<i>=1, packet output ring i is enabled. member in struct:cvmx_sli_pkt_out_enb::cvmx_sli_pkt_out_enb_s
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