| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetMachine.cpp | 43 static StringRef computeDataLayout(const Triple &TT) { argument
52 static Reloc::Model getEffectiveRelocModel(const Triple &TT, argument
59 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcTargetMachine.cpp | 192 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, argument
202 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, argument
212 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, argument
92 SparcTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 167 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) { argument
174 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCTargetDesc.cpp | 77 static MCSubtargetInfo *createMCSubtargetInfo(const Triple &TT, StringRef CPU, argument
37 createMCAsmInfo(const MCRegisterInfo & , const Triple &TT, const MCTargetOptions &Options) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetMachine.cpp | 59 static std::string computeDataLayout(const Triple &TT, StringRef CPU, argument
146 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 35 WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/MCTargetDesc/ |
| H A D | XCoreMCTargetDesc.cpp | 46 static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) { argument
53 createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument
57 createXCoreMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.cpp | 177 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, argument
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| H A D | AArch64TargetMachine.cpp | 193 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { argument
203 static std::string computeDataLayout(const Triple &TT, argument
220 static Reloc::Model getEffectiveRelocModel(const Triple &TT, argument
234 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM, bool JIT) argument
262 AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool LittleEndian) argument
346 AArch64leTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument
354 AArch64beTargetMachine( const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Object/ |
| H A D | IRSymtab.cpp | 82 Triple TT; member in struct:__anon2305::Builder
|
| /freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | LLVMConventionsChecker.cpp | 53 const TypedefType *TT = T->getAs<TypedefType>(); local
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| H A D | NSErrorChecker.cpp | 305 const TypedefType* TT = PPT->getPointeeType()->getAs<TypedefType>(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetMachine.cpp | 104 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { argument
113 computeTargetABI(const Triple &TT, StringRef CPU, argument
131 static std::string computeDataLayout(const Triple &TT, StringRef CPU, argument
188 static Reloc::Model getEffectiveRelocModel(const Triple &TT, argument
207 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool isLittle) argument
303 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument
311 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument
[all...] |
| H A D | ARMSubtarget.cpp | 96 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, argument
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| H A D | ARMBaseInstrInfo.h | 496 TT = 4, // 0b0100 enumerator in enum:llvm::VPTMaskValue
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 52 createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonAsmBackend.cpp | 61 HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI, argument
769 const Triple &TT = STI.getTargetTriple(); local
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsELFObjectWriter.cpp | 689 llvm::createMipsELFObjectWriter(const Triple &TT, bool IsN32) { argument
|
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 136 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { argument
164 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, argument
238 static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/Utils/ |
| H A D | ARMBaseInfo.h | 97 TT = 4, // 0b0100 enumerator in enum:llvm::ARMVCC::VPTMaskValue
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 46 LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, argument
115 LLVMCreateDisasmCPU(const char *TT, cons argument
122 LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp) argument
[all...] |
| /freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 209 MCSubtargetInfo( const Triple &TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | TargetLibraryInfo.cpp | 56 static bool hasBcmp(const Triple &TT) { argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | JITLink.cpp | 291 Error JITLinkContext::modifyPassConfig(const Triple &TT, argument
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| /freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsTargetMachine.cpp | 63 static std::string computeDataLayout(const Triple &TT, StringRef CPU, argument
111 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, argument
140 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, argument
150 MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT) argument
[all...] |