Searched defs:SuperRC (Results 1 - 9 of 9) sorted by relevance
| /freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 435 const TargetRegisterClass *SuperRC = UseDstRC; local
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| H A D | MachineVerifier.cpp | 1790 const TargetRegisterClass *SuperRC = local
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| H A D | RegAllocGreedy.cpp | 2105 const TargetRegisterClass *SuperRC = local
2064 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
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| H A D | TargetLoweringBase.cpp | 1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); local
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 588 const TargetRegisterClass *SuperRC = nullptr; local
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| /freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 407 addSuperRegClass(CodeGenSubRegIndex *SubIdx, CodeGenRegisterClass *SuperRC) argument
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 982 const TargetRegisterClass *SuperRC = local
1124 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local
1177 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local
1228 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local
1290 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local
1362 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local
1524 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); local
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| H A D | AMDGPUISelDAGToDAG.cpp | 596 const TargetRegisterClass *SuperRC = local
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| H A D | SIISelLowering.cpp | 3323 computeIndirectRegAndOffset(const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, unsigned VecReg, int Offset) argument
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