Searched defs:SrcReg (Results 101 - 113 of 113) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64InstructionSelector.cpp	588 const Register SrcReg = I.getOperand(1).getReg(); local 649 Register SrcReg local 620 selectSubregisterCopy(MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register SrcReg, const TargetRegisterClass *From, const TargetRegisterClass *To, unsigned SubReg) argument 675 Register SrcReg = I.getOperand(1).getReg(); local 1265 Register SrcReg = I.getOperand(1).getReg(); local 1677 Register SrcReg = I.getOperand(1).getReg(); local 1756 Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64)); local 2043 const Register SrcReg = I.getOperand(1).getReg(); local 2111 const Register SrcReg = I.getOperand(1).getReg(); local 2158 const Register SrcReg = I.getOperand(1).getReg(); local 2610 Register SrcReg = I.getOperand(2).getReg(); local 2966 const Register SrcReg = I.getOperand(1).getReg(); local 3003 Register SrcReg = I.getOperand(NumElts).getReg(); local 3048 Register SrcReg = I.getOperand(NumElts).getReg(); local 3920 Register SrcReg = I.getOperand(1).getReg(); local 4096 Register SrcReg = I.getOperand(2).getReg(); local [all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonInstrInfo.cpp	787 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const argument 884 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1033 Register SrcReg = MI.getOperand(1).getReg(); local 1043 Register SrcReg = MI.getOperand(1).getReg(); local 1052 Register SrcReg = MI.getOperand(1).getReg(); local 1115 Register SrcReg = MI.getOperand(2).getReg(); local 1765 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument 3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local 3726 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; local [all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A D	ARMISelDAGToDAG.cpp	2200 SDValue SrcReg; local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A D	LegalizerHelper.cpp	841 Register SrcReg = MI.getOperand(0).getReg(); local 1028 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); local 1204 Register SrcReg local 1258 Register SrcReg = MI.getOperand(I).getReg(); local 1304 Register SrcReg = MI.getOperand(NumDst).getReg(); local 1341 Register SrcReg = MI.getOperand(1).getReg(); local 1481 Register SrcReg = MI.getOperand(1).getReg(); local 2166 Register SrcReg = MI.getOperand(0).getReg(); local 2298 Register SrcReg = MI.getOperand(1).getReg(); local 2486 Register SrcReg = MI.getOperand(I).getReg(); local 2549 Register SrcReg = MI.getOperand(1).getReg(); local 3742 Register SrcReg = MI.getOperand(1).getReg(); local 3792 Register SrcReg = MI.getOperand(1).getReg(); local 4139 Register SrcReg = MI.getOperand(1).getReg(); local 4166 const Register SrcReg = MI.getOperand(NumDst).getReg(); local [all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A D	MachineScheduler.cpp	1690 Register SrcReg = SrcOp.getReg(); local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86ISelDAGToDAG.cpp	4790 unsigned SrcReg, LoReg, HiReg; local
H A D	X86InstrInfo.cpp	715 Register SrcReg = Src.getReg(); local 951 Register SrcReg; local 987 Register SrcReg; local 90 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument 1010 Register SrcReg; local 1045 Register SrcReg; local 1094 Register SrcReg; local 1135 Register SrcReg; local 2889 CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget) argument 2965 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const argument 3227 getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) argument 3242 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 3273 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument 3360 isRedundantFlagInstr(const MachineInstr &FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmMask, int ImmValue, const MachineInstr &OI) argument 3550 optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument 4045 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg(); local 4106 Register SrcReg = MIB->getOperand(0).getReg(); local 4118 Register SrcReg = MIB->getOperand(0).getReg(); local 4132 Register SrcReg = MIB->getOperand(0).getReg(); local 7568 Register SrcReg = MI.getOperand(1).getReg(); local [all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	1207 Register SrcReg = MI.getOperand(2).getReg(); local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A D	AMDGPUAsmParser.cpp	2917 const unsigned SrcReg = mc2PseudoReg(Src.getReg()); local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A D	SystemZISelLowering.cpp	6946 Register SrcReg = MI.getOperand(0).getReg(); local 7742 Register SrcReg = MI.getOperand(0).getReg(); local
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A D	ARMAsmParser.cpp	807 unsigned SrcReg; member in struct:__anon2168::ARMOperand::RegShiftedRegOp 814 unsigned SrcReg; member in struct:__anon2168::ARMOperand::RegShiftedImmOp 3460 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, argument 3474 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, argument 3977 int SrcReg = PrevOp->getReg(); local [all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A D	MipsAsmParser.cpp	2670 loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg, bool Is32BitImm, bool IsAddress, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument 2879 loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg, unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) argument 3869 unsigned SrcReg = Inst.getOperand(0).getReg(); local 4359 unsigned SrcReg = SrcRegOp.getReg(); local 4411 unsigned SrcReg = SrcRegOp.getReg(); local 4462 unsigned SrcReg = SrcRegOp.getReg(); local 4512 unsigned SrcReg = Inst.getOperand(1).getReg(); local 4546 unsigned SrcReg = Inst.getOperand(1).getReg(); local 4602 unsigned SrcReg = Inst.getOperand(1).getReg(); local 4652 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5049 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5072 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5114 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5149 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5258 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5284 unsigned SrcReg = Inst.getOperand(1).getReg(); local 5297 DstReg, SrcReg, SrcReg, IDLoc, STI); local [all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	SIISelLowering.cpp	3404 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg(); local [all...]

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Indexes created Sat Jun 08 03:50:41 MDT 2024