| /openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMacroFusion.cpp | 46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, local
|
| H A D | AMDGPUInstCombineIntrinsic.cpp | 44 fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, const APFloat &Src2) argument
[all...] |
| H A D | AMDGPURegBankCombiner.cpp | 281 MachineInstr *Src2 = getDefIgnoringCopies(MI.getOperand(4).getReg(), MRI); local
|
| H A D | GCNDPPCombine.cpp | 321 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); local
654 auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2); local
[all...] |
| H A D | SIShrinkInstructions.cpp | 394 MachineOperand &Src2 = *TII->getNamedOperand(MI, AMDGPU::OpName::src2); local
945 const MachineOperand *Src2 = local
973 const MachineOperand *Src2 local
[all...] |
| H A D | SIOptimizeExecMasking.cpp | 143 const MachineOperand &Src2 = MI.getOperand(2); local
159 const MachineOperand &Src2 = MI.getOperand(2); local
|
| H A D | SIPeepholeSDWA.cpp | 623 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); local
1037 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); local
|
| H A D | AMDGPURegisterBankInfo.cpp | 1572 Register Src2 = MI.getOperand(4).getReg(); local
|
| H A D | AMDGPUISelDAGToDAG.cpp | 2299 SDValue Src2 = N->getOperand(2); local
|
| /openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 152 MachineOperand &Src2 = MI.getOperand(2); local
169 MachineOperand &Src2 = MI.getOperand(2); local
|
| H A D | HexagonGenMux.cpp | 299 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); local
[all...] |
| H A D | HexagonConstPropagation.cpp | 2577 const MachineOperand &Src2 = MI.getOperand(2); local
2598 evaluateHexCompare2(unsigned Opc, const MachineOperand &Src1, const MachineOperand &Src2, const CellMap &Inputs, bool &Result) argument
2634 const MachineOperand &Src2 = MI.getOperand(2); local
[all...] |
| /openbsd-current/gnu/llvm/llvm/lib/ExecutionEngine/Interpreter/ |
| H A D | Execution.cpp | 108 executeFAddInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
119 executeFSubInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
130 executeFMulInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
141 executeFDivInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
152 executeFRemInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument
192 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
206 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
220 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...] |
| /openbsd-current/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 172 EmitTargetCodeForMemcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
224 EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
|
| /openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 57 Register Src2 = MI.getOperand(2).getReg(); local
|
| /openbsd-current/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcAsmPrinter.cpp | 125 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
|
| H A D | SparcISelLowering.cpp | 3074 SDValue Src2 = Op.getOperand(1); local
|
| /openbsd-current/gnu/llvm/llvm/lib/Target/VE/ |
| H A D | VEAsmPrinter.cpp | 153 emitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
|
| /openbsd-current/gnu/llvm/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 518 llvm::Value *Src2 = CGF.EmitScalarExpr(E->getArg(2)); local
577 llvm::Value *Src2 = CGF.EmitScalarExpr(E->getArg(2)); local
[all...] |
| /openbsd-current/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MIPatternMatch.h | 730 Src2Ty Src2; member in struct:llvm::MIPatternMatch::TernaryOp_match
732 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) argument
750 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) { argument
757 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) { argument
|
| H A D | MachineIRBuilder.h | 1742 buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional<unsigned> Flags = std::nullopt) argument
1749 buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional<unsigned> Flags = std::nullopt) argument
|
| /openbsd-current/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 407 unsigned Src2 = UseMI.getOperandNo(UseOp); local
|
| /openbsd-current/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 717 buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef<int> Mask) argument
|
| H A D | CombinerHelper.cpp | 367 Register Src2 = MI.getOperand(2).getReg(); local
|
| /openbsd-current/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2102 SDValue Src2 = ShuffleSrc2 ? ShuffleSrc2 : DAG.getUNDEF(VecT); local
|