| /freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
| H A D | RegisterScavenging.h | 180 void setUsed(BitVector &Regs) { argument
183 void setUnused(BitVector &Regs) { argument
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| H A D | CallingConvLower.h | 281 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { argument
308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { argument
320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, argument
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| /freebsd-10.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.h | 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { argument
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument
150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, argument
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| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 68 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument
[all...] |
| H A D | ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs; local
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| H A D | RegisterPressure.cpp | 109 void RegPressureTracker::increaseRegPressure(ArrayRef<unsigned> Regs) { argument
126 void RegPressureTracker::decreaseRegPressure(ArrayRef<unsigned> Regs) { argument
308 containsReg(ArrayRef<unsigned> Regs, unsigned Reg) argument
341 pushRegUnits(unsigned Reg, SmallVectorImpl<unsigned> &Regs) argument
371 addLiveRegs(ArrayRef<unsigned> Regs) argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 217 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local
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| H A D | RegisterInfoEmitter.cpp | 173 const CodeGenRegister::Set &Regs = RC.getMembers(); local
310 EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument
436 EmitRegMapping(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument
704 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local
1208 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local
1295 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local
[all...] |
| H A D | CodeGenRegisters.cpp | 153 RegUnitIterator(const CodeGenRegister::Set &Regs): argument
981 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local
1241 CodeGenRegister::Set Regs; member in struct:__anon3651::UberRegSet
1272 const CodeGenRegister::Set &Regs = RegClass->getMembers(); local
1874 computeCoveredRegisters(ArrayRef<Record*> Regs) argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 191 SmallVector<SDValue, 4> Regs; local
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| H A D | R600InstrInfo.cpp | 612 std::vector<unsigned> Regs; local
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| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 590 SmallVector<std::pair<unsigned,bool>, 4> Regs; local
660 SmallVector<unsigned, 4> Regs; local
[all...] |
| H A D | ARMLoadStoreOptimizer.cpp | 393 SmallVector<std::pair<unsigned, bool>, 8> Regs; local
282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 447 parseRegister(Register &Reg, char Prefix, const unsigned *Regs, bool IsAddress) argument
469 parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands, char Prefix, const unsigned *Regs, SystemZOperand::RegisterKind Kind, bool IsAddress) argument
486 parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands, const unsigned *Regs, SystemZOperand::RegisterKind RegKind, bool HasIndex) argument
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | LoopStrengthReduce.cpp | 839 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument
887 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
903 RateFormula(const Formula &F, SmallPtrSet<const SCEV *, 16> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument
1160 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon2649::LSRUse
3663 SmallPtrSet<const SCEV *, 16> Regs; local
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 602 SmallVector<unsigned, 4> Regs; member in struct:__anon2224::RegsForValue
5741 SmallVector<unsigned, 4> Regs; local
[all...] |
| /freebsd-10.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2231 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, argument
|