| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); local
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| H A D | WebAssemblyRegStackify.cpp | 106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); local
645 const auto *RegClass = MRI.getRegClass(Reg); local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; member in class:llvm::RegisterClassInfo
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| H A D | RegisterScavenging.h | 166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj, argument
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| H A D | RDFRegisters.h | 136 const TargetRegisterClass *RegClass = nullptr; member in struct:llvm::rdf::PhysicalRegisterInfo::RegInfo
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); local
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| H A D | MachineRegisterInfo.cpp | 158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, argument
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| H A D | LiveIntervals.cpp | 1713 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); local
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| H A D | TargetInstrInfo.cpp | 53 short RegClass = MCID.OpInfo[OpNum].RegClass; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVEVPTOptimisationsPass.cpp | 140 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg); local
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| H A D | ARMBaseRegisterInfo.cpp | 823 const TargetRegisterClass *RegClass = local
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| H A D | ARMLoadStoreOptimizer.cpp | 583 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { argument
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| H A D | ARMFrameLowering.cpp | 1547 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF); local
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| H A D | ARMISelDAGToDAG.cpp | 1825 SDValue RegClass = local
1836 SDValue RegClass = local
1847 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, local
1858 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, local
1870 SDValue RegClass = local
1885 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, local
1900 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, local
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 2493 const TargetRegisterClass *RegClass; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RISCVCompressInstEmitter.cpp | 140 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 88 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); local
31 constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass) argument
41 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO) argument
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 309 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
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| H A D | FastISel.cpp | 2082 const TargetRegisterClass *RegClass = local
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 80 int16_t RegClass; member in class:llvm::MCOperandInfo
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AsmPrinter.cpp | 717 const TargetRegisterClass *RegClass; local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 581 int RegClass = Desc.OpInfo[OpIdx].RegClass; local
656 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); local
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| H A D | SIInstrInfo.cpp | 868 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); local
3555 int RegClass = Desc.OpInfo[i].RegClass; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4269 unsigned RegClass = getMaskRC(MaskVT); local
4307 unsigned RegClass = getMaskRC(ResVT); local
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7348 const TargetRegisterClass *RegClass = local
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