/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 248 unsigned Reg0 = Op0.getReg(); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 226 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 658 unsigned Reg0 = MI->getOperand(0).getReg(); local
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H A D | ARMAsmPrinter.cpp | 301 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); local
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H A D | ARMISelDAGToDAG.cpp | 1862 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 1989 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2153 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2249 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2352 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2587 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2604 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 3839 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 440 unsigned Reg0 = local 458 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); local
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/freebsd-11.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 599 uint16_t Reg0; member in class:llvm::MCRegUnitRootIterator
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 348 unsigned Reg0 = MI->getOperand(0).getReg(); local 378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); local
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetInstrInfo.cpp | 139 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
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H A D | RegisterCoalescer.cpp | 1891 unsigned Reg0; local
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/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 5636 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1438 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc, argument 1448 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc, argument 1453 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc, argument 1468 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, argument 1477 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2, argument 1488 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument 1494 emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) argument [all...] |