Lines Matching defs:Reg0

1862   SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1874 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1882 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1885 Ops.push_back(Reg0);
1898 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1911 Ops.push_back(Reg0);
1915 Ops.push_back(Reg0);
1989 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2025 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
2034 Ops.push_back(Reg0);
2038 Ops.push_back(Reg0);
2062 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2077 Ops.push_back(Reg0);
2081 Ops.push_back(Reg0);
2153 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2160 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2184 Ops.push_back(Reg0);
2249 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2263 Ops.push_back(Reg0);
2266 Ops.push_back(Reg0);
2352 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2360 getAL(CurDAG, dl), Reg0, Reg0 };
2370 getAL(CurDAG, dl), Reg0, Reg0 };
2377 getAL(CurDAG, dl), Reg0 };
2396 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2400 getAL(CurDAG, dl), Reg0 };
2415 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2419 getAL(CurDAG, dl), Reg0 };
2587 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2589 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2592 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2593 Reg0 };
2604 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2606 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG, dl), Reg0, Reg0 };
2609 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG, dl), Reg0,
2610 Reg0 };
3839 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3862 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3877 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,