Searched defs:Reg (Results 1 - 25 of 166) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DAllocationOrder.h56 unsigned Reg = *Pos++; local
H A DRegAllocBase.cpp71 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
H A DDeadMachineInstructionElim.cpp69 unsigned Reg = MO.getReg(); local
106 unsigned Reg = *LOI; local
136 unsigned Reg = MO.getReg(); local
164 unsigned Reg = MO.getReg(); local
183 unsigned Reg = MO.getReg(); local
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H A DProcessImplicitDefs.cpp78 unsigned Reg = MI->getOperand(0).getReg(); local
H A DCallingConvLower.cpp59 void CCState::MarkAllocated(unsigned Reg) { argument
H A DLiveRangeCalc.cpp38 void LiveRangeCalc::createDeadDefs(LiveInterval *LI, unsigned Reg) { argument
62 void LiveRangeCalc::extendToUses(LiveInterval *LI, unsigned Reg) { argument
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H A DMachineCopyPropagation.cpp63 MachineCopyPropagation::SourceNoLongerAvailable(unsigned Reg, argument
230 unsigned Reg = MO.getReg(); local
262 unsigned Reg local
279 unsigned Reg = Defs[i]; local
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H A DTargetSchedule.cpp248 unsigned Reg = DefMI->getOperand(DefOperIdx).getReg(); local
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h38 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
44 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMBaseRegisterInfo.h38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { argument
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { argument
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { argument
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H A DARMCallingConv.h78 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); local
123 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); local
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonMachineFunctionInfo.h43 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
H A DHexagonCallingConvLower.cpp58 void Hexagon_CCState::MarkAllocated(unsigned Reg) { argument
101 unsigned Reg = Hexagon::R0; local
107 unsigned Reg = Hexagon::D0; local
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp196 unsigned Reg = CSI[i-1].getReg(); local
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMips16FrameLowering.cpp83 unsigned Reg = CSI[i].getReg(); local
H A DMipsMachineFunction.h66 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
H A DMipsSERegisterInfo.cpp123 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm); local
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86FloatingPoint.cpp118 unsigned Reg = *I - X86::FP0; local
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h151 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument
170 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument
195 unsigned Reg = It->second; local
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H A DLiveVariables.h283 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
301 isPHIJoin(unsigned Reg) argument
304 setPHIJoin(unsigned Reg) argument
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/
H A DMCWin64EH.h36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg) argument
43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off) argument
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/
H A DTargetFrameLowering.h43 unsigned Reg; member in struct:llvm::TargetFrameLowering::SpillSlot
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUFrameLowering.cpp170 unsigned Reg = CSI[I].getReg(); local
H A DSPURegisterInfo.cpp352 unsigned Reg = RS->FindUnusedReg(RC); local

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