| /freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXInstPrinter.cpp | 82 unsigned Reg = Op.getReg(); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 196 Register Reg; local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 38 unsigned Reg = WebAssembly::UnusedReg; local
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| H A D | WebAssemblyRegColoring.cpp | 143 Register Reg = LI->reg(); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86IntelInstPrinter.cpp | 483 unsigned Reg = Op.getReg(); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcInstPrinter.cpp | 45 void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg, argument
119 unsigned Reg = MO.getReg(); local
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| H A D | SparcMCTargetDesc.cpp | 47 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); local
57 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRangeShrink.cpp | 178 Register Reg = MO.getReg(); local
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| H A D | AggressiveAntiDepBreaker.cpp | 70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { argument
114 IsLive(unsigned Reg) argument
158 unsigned Reg = *AI; local
172 unsigned Reg = *I; local
[all...] |
| H A D | MachineLoopInfo.cpp | 213 Register Reg = MO.getReg(); local
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| H A D | MachineLateInstrsCleanup.cpp | 46 bool hasIdentical(Register Reg, MachineInstr *ArgMI) { argument
119 clearKillsForDef(Register Reg, MachineBasicBlock *MBB, argument
145 Register Reg = MI->getOperand(0).getReg(); local
229 Register Reg = DefI.first; local
[all...] |
| H A D | LiveIntervalCalc.cpp | 53 Register Reg = LI.reg(); local
123 void LiveIntervalCalc::createDeadDefs(LiveRange &LR, Register Reg) { argument
135 extendToUses(LiveRange &LR, Register Reg, LaneBitmask Mask, LiveInterval *LI) argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Localizer.cpp | 93 Register Reg = MI.getOperand(0).getReg(); local
161 Register Reg = MI->getOperand(0).getReg(); local
|
| /freebsd-current/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | LoongArch.cpp | 61 enum Reg { enum in namespace:__anon1298
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 177 unsigned Reg = RegMask.PhysReg; local
198 Register Reg = MO.getReg(); local
[all...] |
| H A D | X86InstrBuilder.h | 49 unsigned Reg; member in union:llvm::X86AddressMode::__anon4490
124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
132 setDirectAddressInInstr(MachineInstr *MI, unsigned Operand, unsigned Reg) argument
157 addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset) argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 410 O << LS << Reg; local
428 O << LS << Reg; local
[all...] |
| /freebsd-current/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | Taint.cpp | 158 bool taint::isTainted(ProgramStateRef State, const MemRegion *Reg, argument
187 getTaintedSymbols(ProgramStateRef State, const MemRegion *Reg, TaintTagType Kind) argument
212 getTaintedSymbolsImpl(ProgramStateRef State, const MemRegion *Reg, TaintTagType K, bool returnFirstOnly) argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | BitTracker.h | 134 Register Reg; member in struct:llvm::BitTracker::BitRef
146 Register Reg; member in struct:llvm::BitTracker::RegisterRef
196 BitValue(unsigned Reg, uint16_t Pos) argument
[all...] |
| H A D | HexagonBlockRanges.h | 36 llvm::Register Reg; member in struct:llvm::HexagonBlockRanges::RegisterRef
|
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 223 unsigned Reg = Entry.getReg(); local
450 emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned Reg, int NumBytes, bool IsAdd, const ARCInstrInfo *TII) argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg, argument
113 static bool isFPR64(unsigned Reg, unsigned SubReg, argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600OptimizeVectorRegisters.cpp | 40 static bool isImplicitlyDef(MachineRegisterInfo &MRI, Register Reg) { argument
184 Register Reg = RSI->Instr->getOperand(0).getReg(); local
332 Register Reg = MI.getOperand(1).getReg(); local
345 Register Reg = MI.getOperand(0).getReg(); local
[all...] |
| H A D | R600MachineScheduler.cpp | 203 bool R600SchedStrategy::regBelongsToClass(Register Reg, argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 79 unsigned Reg = GR8DecoderTable[RegNo]; local
97 unsigned Reg = GR16DecoderTable[RegNo]; local
131 unsigned Reg = Bits & 15; local
|