| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 36 const TargetRegisterClass *RC; local
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| H A D | Mips16InstrInfo.cpp | 83 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
99 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| H A D | MipsSEFrameLowering.cpp | 179 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); local
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| H A D | LiveStackAnalysis.cpp | 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
80 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
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| H A D | AggressiveAntiDepBreaker.h | 45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon9926
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| H A D | CriticalAntiDepBreaker.cpp | 592 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; local
375 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC) argument
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| H A D | LocalStackSlotAllocation.cpp | 318 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); local
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| H A D | MachineRegisterInfo.cpp | 45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
50 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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| H A D | PHIElimination.cpp | 238 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); local
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| H A D | PeepholeOptimizer.cpp | 263 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); local
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| H A D | RegisterScavenging.cpp | 243 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument
323 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, argument
[all...] |
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/ |
| H A D | SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, argument
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| H A D | SPUFrameLowering.cpp | 252 const TargetRegisterClass *RC = &SPU::R32CRegClass; local
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| H A D | SPURegisterInfo.cpp | 346 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) const argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| H A D | Thumb2InstrInfo.cpp | 125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
152 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...] |
| /macosx-10.10.1/llvmCore-3425.0.34/utils/TableGen/ |
| H A D | FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC; member in struct:__anon10626::InstructionMemo
[all...] |
| /macosx-10.10.1/mDNSResponder-561.1.1/mDNSWindows/Java/ |
| H A D | makefile | 40 RC = rc macro
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/ |
| H A D | MBlazeInstrInfo.cpp | 93 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
103 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
62 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) { argument
93 getNVPTXRegClassStr(TargetRegisterClass const *RC) argument
154 isNVPTXVectorRegClass(TargetRegisterClass const *RC) argument
178 getNVPTXElemClassName(TargetRegisterClass const *RC) argument
202 getNVPTXElemClass(TargetRegisterClass const *RC) argument
226 getNVPTXVectorSize(TargetRegisterClass const *RC) argument
[all...] |
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
| H A D | X86VZeroUpper.cpp | 147 const TargetRegisterClass *RC = &X86::VR256RegClass; local
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| /macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 133 const TargetRegisterClass *RC = 0; local
218 const TargetRegisterClass *RC = local
275 const TargetRegisterClass *RC local
[all...] |
| H A D | ScheduleDAGSDNodes.cpp | 127 const TargetRegisterClass *RC = local
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