| /freebsd-current/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVRegisterBankInfo.cpp | 28 SPIRVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupSetCC.cpp | 101 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() local
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| H A D | X86ArgumentStackSlotRebase.cpp | 74 const TargetRegisterClass *RC = nullptr; local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyReplacePhysRegs.cpp | 83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveStacks.cpp | 54 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
79 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
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| H A D | RegisterBank.cpp | 26 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); local
92 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); local
[all...] |
| H A D | RegAllocBase.cpp | 127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg->reg()); local
184 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); local
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| H A D | MIRVRegNamerUtils.cpp | 171 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 45 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
63 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
76 const TargetRegisterClass &RC = XCore::GRRegsRegClass; local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| H A D | WebAssemblyMCTypeUtilities.cpp | 105 wasm::ValType WebAssembly::regClassToValType(unsigned RC) { argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVDeadRegisterDefinitions.cpp | 87 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); local
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| H A D | RISCVRVVInitUndef.cpp | 110 const TargetRegisterClass *RC = MRI->getRegClass(R); local
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 41 const auto RC = MRI.getRegClass(Reg); local
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| H A D | AMDGPUISelLowering.h | 328 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const argument
335 CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, Register Reg, EVT VT) const argument
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| H A D | GCNPreRAOptimizations.cpp | 231 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstantFolder.h | 46 auto *RC = dyn_cast<Constant>(RHS); variable
58 auto *RC = dyn_cast<Constant>(RHS); variable
71 auto *RC = dyn_cast<Constant>(RHS); variable
100 auto *RC = dyn_cast<Constant>(RHS); variable
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kRegisterBankInfo.cpp | 62 M68kRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, argument
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| /freebsd-current/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | TargetFolder.h | 57 auto *RC = dyn_cast<Constant>(RHS); variable
69 auto *RC = dyn_cast<Constant>(RHS); variable
82 auto *RC = dyn_cast<Constant>(RHS); variable
104 auto *RC = dyn_cast<Constant>(RHS); variable
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 51 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | BitTracker.cpp | 115 raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { argument
165 OS << "]:" << RC[Start]; local
201 bool BT::RegisterCell::meet(const RegisterCell &RC, Registe argument
214 insert(const BT::RegisterCell &RC, const BitMask &M) argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | Mips16RegisterInfo.cpp | 56 saveScavengerRegister( MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const argument
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| /freebsd-current/crypto/openssl/crypto/whrlpool/ |
| H A D | wp_block.c | 486 #define RC (&(Cx.q[256*N])) macro
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64DeadRegisterDefinitionsPass.cpp | 159 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); local
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
65 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument
[all...] |
| /freebsd-current/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenIntrinsics.cpp | 28 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { argument
|