1//===-- M68kRegisterBankInfo.cpp --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the RegisterBankInfo class for M68k.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "M68kRegisterBankInfo.h"
14#include "M68kInstrInfo.h" // For the register classes
15#include "M68kSubtarget.h"
16#include "llvm/CodeGen/MachineRegisterInfo.h"
17#include "llvm/CodeGen/RegisterBank.h"
18#include "llvm/CodeGen/RegisterBankInfo.h"
19#include "llvm/CodeGen/TargetRegisterInfo.h"
20
21#define GET_TARGET_REGBANK_IMPL
22#include "M68kGenRegisterBank.inc"
23
24using namespace llvm;
25
26// FIXME: TableGen this.
27// If it grows too much and TableGen still isn't ready to do the job, extract it
28// into an M68kGenRegisterBankInfo.def (similar to AArch64).
29namespace llvm {
30namespace M68k {
31enum PartialMappingIdx {
32  PMI_GPR,
33  PMI_Min = PMI_GPR,
34};
35
36const RegisterBankInfo::PartialMapping PartMappings[]{
37    // GPR Partial Mapping
38    {0, 32, GPRRegBank},
39};
40
41enum ValueMappingIdx {
42  InvalidIdx = 0,
43  GPR3OpsIdx = 1,
44};
45
46const RegisterBankInfo::ValueMapping ValueMappings[] = {
47    // invalid
48    {nullptr, 0},
49    // 3 operands in GPRs
50    {&PartMappings[PMI_GPR - PMI_Min], 1},
51    {&PartMappings[PMI_GPR - PMI_Min], 1},
52    {&PartMappings[PMI_GPR - PMI_Min], 1},
53
54};
55} // end namespace M68k
56} // end namespace llvm
57
58M68kRegisterBankInfo::M68kRegisterBankInfo(const TargetRegisterInfo &TRI)
59    : M68kGenRegisterBankInfo() {}
60
61const RegisterBank &
62M68kRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
63                                             LLT) const {
64  return getRegBank(M68k::GPRRegBankID);
65}
66
67const RegisterBankInfo::InstructionMapping &
68M68kRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
69  auto Opc = MI.getOpcode();
70
71  if (!isPreISelGenericOpcode(Opc)) {
72    const InstructionMapping &Mapping = getInstrMappingImpl(MI);
73    if (Mapping.isValid())
74      return Mapping;
75  }
76
77  using namespace TargetOpcode;
78
79  unsigned NumOperands = MI.getNumOperands();
80  const ValueMapping *OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
81
82  switch (Opc) {
83  case G_ADD:
84  case G_SUB:
85  case G_MUL:
86  case G_SDIV:
87  case G_UDIV:
88  case G_LOAD:
89  case G_STORE: {
90    OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
91    break;
92  }
93
94  case G_CONSTANT:
95  case G_FRAME_INDEX:
96    OperandsMapping =
97        getOperandsMapping({&M68k::ValueMappings[M68k::GPR3OpsIdx], nullptr});
98    break;
99  default:
100    return getInvalidInstructionMapping();
101  }
102
103  return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
104                               NumOperands);
105}
106