Searched defs:RC (Results 201 - 225 of 256) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp2299 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; local
2505 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
2680 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
H A DPPCFastISel.cpp448 PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, const TargetRegisterClass *RC, bool IsZExt, unsigned FP64LoadOpc) argument
606 const TargetRegisterClass *RC = local
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); local
987 auto RC = MRI.getRegClass(SrcReg); local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass; local
1174 const TargetRegisterClass *RC = local
1225 auto RC = MRI.getRegClass(SrcReg); local
1280 const TargetRegisterClass *RC = local
1442 const TargetRegisterClass *RC = local
1454 const TargetRegisterClass *RC = local
1768 const TargetRegisterClass *RC = local
1777 const TargetRegisterClass *RC = local
1925 const TargetRegisterClass *RC = local
2000 const TargetRegisterClass *RC; local
2061 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass; local
2118 PPCMaterialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2150 PPCMaterialize64BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2221 const TargetRegisterClass *RC = local
2403 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass : local
2422 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm) argument
2441 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0) argument
2454 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, unsigned Op0, unsigned Op1) argument
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp277 const auto *RC = TRI->getRegClass(I); local
1573 const TargetRegisterClass *RC = PFS.Target.getRegClass(Name); local
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/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp880 getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy) argument
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineFunction.cpp710 addLiveIn(MCRegister PReg, const TargetRegisterClass *RC) argument
H A DMachineLICM.cpp889 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
1313 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); local
H A DModuloSchedule.cpp545 const TargetRegisterClass *RC = MRI.getRegClass(Def); local
684 const TargetRegisterClass *RC = MRI.getRegClass(Def); local
1034 const TargetRegisterClass *RC = MRI.getRegClass(reg); local
1446 auto RC = MRI.getRegClass(Reg); local
1463 phi(Register LoopReg, std::optional<Register> InitReg, const TargetRegisterClass *RC) argument
1520 undef(const TargetRegisterClass *RC) argument
1649 auto RC = MRI.getRegClass(PhiR); local
1866 auto RC = MRI.getRegClass(MI.getOperand(0).getReg()); local
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H A DMachineVerifier.cpp2241 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg); local
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h71 const TargetRegisterClass *RC; member in union:llvm::DstOp::__anon1607
/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp991 CodeGenRegisterClass &RC = *I; local
1279 CodeGenRegisterClass &RC = RegClasses.back(); local
1331 addToMaps(CodeGenRegisterClass *RC) argument
1343 getOrCreateSubClass(const CodeGenRegisterClass *RC, const CodeGenRegister::Vec *Members, StringRef Name) argument
2228 inferCommonSubClass(CodeGenRegisterClass *RC) argument
2268 inferSubClassWithSubReg(CodeGenRegisterClass *RC) argument
2318 inferMatchingSuperRegClass(CodeGenRegisterClass *RC, std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) argument
2400 CodeGenRegisterClass *RC = &*I; local
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H A DGlobalISelEmitter.cpp1090 const CodeGenRegisterClass *RC = local
1829 const CodeGenRegisterClass &RC local
1834 const CodeGenRegisterClass &RC = Target.getRegisterClass(DstIOpRec); local
1857 auto RC = local
1956 const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp1023 const TargetRegisterClass *RC = &X86::GR32RegClass; local
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H A DX86FastISel.cpp464 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
769 const TargetRegisterClass *RC = nullptr; local
1790 const TargetRegisterClass *RC = nullptr; local
1874 const TargetRegisterClass *RC; member in struct:DivRemEntry
2033 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2193 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2336 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2363 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local
2433 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); local
2451 X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned TargetOpc, const TargetRegisterClass *RC) argument
2608 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); local
2667 const TargetRegisterClass *RC = nullptr; local
2821 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
3044 const TargetRegisterClass *RC = nullptr; local
3163 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
3946 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); local
4035 fastEmitInst_rrrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2, unsigned Op3) argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp564 const TargetRegisterClass *RC = local
591 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local
882 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
897 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
1222 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass); local
1603 getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp706 const TargetRegisterClass *RC = local
832 const TargetRegisterClass *RC = nullptr; local
3445 const TargetRegisterClass *RC = MRI.getRegClass(OffsetReg); local
4765 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
4948 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2036 SDValue RC = CurDAG->getTargetConstant(InRegClassID, DL, XLenVT); local
2080 SDValue RC = CurDAG->getTargetConstant(InRegClassID, DL, XLenVT); local
H A DRISCVInstrInfo.cpp596 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
679 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
2078 auto *RC = MRI.getRegClass(Op.getReg()); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp125 const TargetRegisterClass *RC = TRI.getPhysRegBaseClass(SuperReg); local
200 const TargetRegisterClass &RC = local
447 SIRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
1340 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); local
2345 const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass local
2439 const TargetRegisterClass *RC = IsSALU && !LiveSCC local
2598 getRegBitWidth(const TargetRegisterClass &RC) argument
2863 const TargetRegisterClass *RC; local
2950 findUnusedRegister( const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestRegister) const argument
2975 getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const argument
3005 const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); local
3012 const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); local
3039 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const argument
3267 getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const argument
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp296 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0) argument
318 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1) argument
345 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm) argument
370 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
462 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local
478 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local
531 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local
657 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); local
831 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local
904 const TargetRegisterClass *RC; local
1472 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local
1644 const TargetRegisterClass *RC; local
2495 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local
2693 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; local
3062 const TargetRegisterClass *RC = &ARM::rGPRRegClass; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp310 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument
364 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { argument
3025 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
3094 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
3509 const TargetRegisterClass *RC = local
3561 const TargetRegisterClass *RC = local
3808 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; local
3837 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp718 LatticeCell RC = Cells.get(DefR.Reg); local
1390 LatticeCell RC; local
1079 getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC) argument
1406 LatticeCell RC; local
1457 LatticeCell RC; local
1473 LatticeCell RC; local
1522 LatticeCell RC; local
1941 LatticeCell RC; local
1963 LatticeCell RC; local
1997 LatticeCell RC = Outputs.get(DefR.Reg); local
2006 LatticeCell RC = Outputs.get(DefR.Reg); local
2040 LatticeCell RC = Outputs.get(DefR.Reg); local
2052 LatticeCell RC = Outputs.get(DefR.Reg); local
2101 LatticeCell RC = Outputs.get(DefR.Reg); local
2133 LatticeCell RC = Outputs.get(DefR.Reg); local
2155 LatticeCell RC = Outputs.get(DefR.Reg); local
2208 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg); local
2360 const TargetRegisterClass *RC = MRI->getRegClass(Reg); local
2636 LatticeCell RC; local
2693 LatticeCell RC = Outputs.get(DefR.Reg); local
2752 LatticeCell RC = Outputs.get(DefR.Reg); local
2767 LatticeCell RC = Outputs.get(DefR.Reg); local
2867 const TargetRegisterClass *RC = MRI->getRegClass(R); local
2994 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
3023 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
3060 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
3092 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg); local
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H A DHexagonISelLowering.cpp842 const TargetRegisterClass *RC = getRegClassFor(RegVT); local
H A DHexagonFrameLowering.cpp1421 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local
1485 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local
1668 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); local
1680 const TargetRegisterClass *RC local
1527 needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) argument
1815 auto *RC = &Hexagon::HvxVRRegClass; local
1851 auto *RC = &Hexagon::HvxVRRegClass; local
2183 const TargetRegisterClass *RC = nullptr; member in struct:SlotInfo
2245 auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF); local
2413 auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF); local
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2030 const TargetRegisterClass *RC = &VE::I64RegClass; local
2080 const TargetRegisterClass *RC = &VE::I64RegClass; local
2196 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); local
2499 const TargetRegisterClass *RC = &VE::I64RegClass; local
3066 const TargetRegisterClass *RC = nullptr; local
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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1103 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument
1121 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const argument

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1234567891011